( ESNUG 395 Item 12 ) -------------------------------------------- [06/26/02]
Subject: ( SNUG 02 #7 ) SystemC Sucks -- Stop Comparing Superlog & SystemC
> Superlog Superlog Superlog. By the time SystemC is done, it combines all
> the disadvantages of C (a contrived event model and no concept of time)
> with all the disadvantages of HDLs (runtime "challenges" -- continental
> drift anyone on a 70+ million transistor design? -- and a lack of high
> level abstraction mechanisms.) Superlog addresses these in a much
> cleaner way.
>
> In addition, it's high time to dispel the myth of if we can use C to
> design ASICs, then C programmers can be ASIC designers. That's BS.
>
> - Tom Heynemann of Compaq
From: Nick Skelton <nick.skelton@freehand.se>
Hi John,
You're misfiling Superlog by lumping it into threads about SystemC. Surely
everyone has now seen that design in C is not going to fly. You should be
listing Superlog with the verification languages like E and Vera.
In design and especially sub block verification, Superlog is good. The
subblock designers, who really want have have access to all the
verification features, don't want to have to learn a new weird language.
We've been using Superlog Systemsim for 3 years now. We like
it. It's robust and fast, can't do VHDL, but it does simulate C together
with Verilog and Superlog rather well. We use that a lot.
- Nick Skelton
Freehand DSP AB Sweden
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