( ESNUG 396 Item 6 ) --------------------------------------------- [07/11/02]
From: Larry Hudepohl <lhh@mips.com>
Subject: MIPS Reviews The Synopsys coreBuilder & coreConsultant DW IP Tools
Hi John,
My group at MIPS has been working on the DW-4KE family of DW parts.
We've been using the Synopsys coreBuilder tool so that a MIPS customer
could use our parts simply through the Synopsys coreConsultant tool.
Here are our benchmarks from trying to get our IP through coreBuilder.
Scan. We only support the Mentor test tools with our version of the MIPS
4KE cores. DFT Advisor for scan insertion and FastScan for ATPG. So we
didn't have any experience with the Synopsys test tools. Synopsys's
coreBuilder provides automation and scripts for their testability tools,
DFTCompiler and TetraMax.
FYI: Verilog/VHDL simulation seems to be the only place where Synopsys
coreBuilder acknowledges the existence of rival tools. It supports
simulators from Cadence and Mentor. Third party support for other tools
(synthesis, STA, DFT, and power analysis) is not included in coreBuilder.
We found that the Synopsys test tools yielded very good results compared
to the Mentor tools on our 4KE cores. TetraMax achieved better test
coverage in about 27% fewer vectors than FastScan.
ATPG tool Test coverage Vectors
--------- ------------- -------
FastScan 98.94% 1062
TetraMax 99.36% 773
The data above compares two identically configured 4KEc core netlists. One
had scan insertion performed by Mentor DFT Advisor after synthesis with DC,
then ATPG performed by FastScan (version 8.9_2.10). In the second case,
scan insertion was done by Synopsys DFT Compiler during DC synthesis, then
ATPG was run with TetraMax (version 2001.08).
Gated clocks and Power Compiler. The coreConsultant tool includes direct
hooks for Design Compiler synthesis with Power Compiler power optimizations.
(Remember that coreBuilder is what we used to package our MIPS IP. Our
customers then use coreConsultant to customize our MIPS core in their
designs.) The power savings is from it replacing conditional flops in our
MIPS core with gated flops. Power Compiler lets our customers dynamically
trade-off the amount of clock gating within the MIPS core by choosing the
threshold for how many flops are controlled by the same condition. (This is
all before clock gating is employed.)
Here is a table showing some results for various thresholds, all based on
our MIPS DW-4KEc core in a maximum configuration, containing a total of
8688 flops. These runs used an Artisan 0.18um G library and were
synthesized using Design Compiler and Power Compiler (version 2001.08),
under coreConsultant (version 3.1.3).
Case # Gated # Unique Relative Relative Power
Flops Cond Area Period (mw/MHz)
------------------------------------------------------------
No PowerComp 0 0 1.00 1.00 1.70
thresh = 16 6598 231 0.87 1.01 0.80
thresh = 8 7284 305 0.89 1.01 0.69
thresh = 4 7722 396 0.86 0.97 0.59
thresh = 2 7789 422 0.85 0.98 0.57
thresh = 1 7949 583 0.86 1.00 0.59
The "Gated Flops" column shows how many flops Power Compiler identified for
gating, while the next column shows the number of clock gating elements
needed. The "Relative Area" shows the area improvement with clock gating,
normalized to the case where Power Compiler was not run. The "Relative
Period" column indicates minimal impact on cycle time. The "Power" column
shows absolute average power dissipation, from PrimePower analysis while
simulating a Dhrystone 2.1 benchmark at 1.8 v.
- Larry Hudepohl
MIPS Technologies, Inc. Mountain View, CA
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