( ESNUG 396 Item 9 ) --------------------------------------------- [07/11/02]
Subject: ( ESNUG 395 #9 ) VHDL <-> Verilog Or Vera <-> Verisity Xslators
> What vendors out there are offering translators for VHDL <-> Verilog or
> Vera <-> Verisity?
>
> - Bill Billowitch
> Agere Systems Allentown, PA
From: Thomas Bollaert <tbollaert@sd.com>
Hi John,
Summit Design provides VHDL <-> Verilog translation as well as design
documentation and design reuse features as part of our Visual Elite
design environment.
- Thomas Bollaert
Summit Design Cergy Pontoise, France
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From: janick@qualis.com (Janick Bergeron)
Hi, John,
It is very unlikely one would be able to translate Vera <-> e. The two
languages are just too different in their approach.
VHDL and Verilog are *much* simpler in their syntax and semantics, yet one
cannot find a translator that supports anything beyond the RTL subset (which
is *really* simple).
- Janick Bergeron
Qualis Design
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