( ESNUG 397 Item 1 ) --------------------------------------------- [07/24/02]
Subject: ( ESNUG 395 #2 ) Vectored Busses Mess With Cadence's pwrAnalysis
> Does anybody else use Cadence's power analysis/IR tool, "pwrAnalysis" ?
> We've been trying to use it here, but have been running into brick walls.
> The bugs that we've uncovered have seemed so elementary, so basic, that it
> makes me wonder just how many other chip companies are using this tool.
> I'm suspicious that we're the only ones.
>
> What we're stuck on at the moment is that the tool can't handle VCD toggle
> files with busses. Everything has to be scalar. Yes, I know, you're
> thinking "what real-world design doesn't use busses?" Well, whatever
> design that Cadence uses to regression test their code apparently doesn't.
>
> - Rob Stalker
> XtremeSpectrum, Inc. Vienna, VA
From: Geoff Smith <gjsmith@cisco.com>
Hi, John,
Cadence's pwrAnalysis was bad and buggy when we we tried it (1.5 years ago).
In fact our experience was so bad that we refuse to waste time on it any
more. It clearly had zero regression tests or any QA worthy of the name.
A good engineer would have hung their head in shame at releasing such a
product.
Not helping the situation at the time was the inability of the library to
keep up with providing energy data in the TLF format required. Cadence's
penchant for continuously redefining TLF in a non-backward compatible
manner causes major pain.
The TLF energy format required by Cadence's LPS tool wasn't compatible
with the energy format required by Cadence's pwrAnalysis tool. What kind
of B.S. is that!
Things may have improved since then but once bitten, twice shy. We
currently use an internally developed tool for power analysis.
- Geoff Smith
Cisco Systems Inc. Toowong, Australia
---- ---- ---- ---- ---- ---- ----
From: [ An Ex-Cadence pwrAnalysis Developer ]
Hi John,
Concerning Cadence's pwrAnalysis, I was a developer there before and would
like to offer a workaround. Since I no longer work at Cadence, please keep
me anonymous.
Cadence's pwrAnalysis uses LEF/DEF as its netlist. Since it uses physical
netlist and it may have some problems mapping logical netlist (especially
if you dump VCD from logical netlist from synthesis tools). When SE reads
logical Verilog it dismantles buses into different nets. PwrAnalysis' VCD
parser would need to work harder to discern the physical net vs logical net
since it reads LEF/DEF from SE.
I recommend that users use SE to output a physical Verilog and dump VCD with
a physical Verilog. It is safer because after buffer insertion and other SE
optimization, the physical netlist may be very different from original
logical netlist if you decide to run the tool at the very late stage of the
design cycle.
Also it requires a VCD that contains all switching information of every nets
in a design not just I/O.
I hope that helps.
- [ An Ex-Cadence pwrAnalysis Developer ]
---- ---- ---- ---- ---- ---- ----
From: Ankur Gupta <ankur@cadence.com>
Hi John,
Most of our other users are not using the same pwrAnalysis flow as
XtremeSpectrum, involving Signalscan which keeps the busses vectored.
Cadence's pwrAnalysis measures static and dynamic power consumption, and
checks power line integrity through IR Drop and Electromigration analysis.
It is a gate level tool, requiring power models in Liberty or TLF format.
Integrated within Silicon Ensemble, it can obtain signal line parasitic and
slew information directly from SE or through file inputs. It also requires
signal switching activity. VCD files are used to perform a time-varying
dynamic power simulation. It can also be used to extract per-net activity
for average power computation, which is what Rob Stalker attempted.
As far as busses are concerned, we do support them. The use model requires
that in the VCD file, the bus be expanded into scalar bits. Simulators
like Verilog-XL allow this. Let's say, Verilog file has the commands:
$dumpfile(test.vcd);
$dumpvars...
1. Using Verilog-XL, use the '-x' option to expand busses
verilog -x <verilog files>
2. Using 'ncsim', use the -expand option
ncvlog ...
ncelab -expand ...
ncsim ...
3. Using 'ncverilog', use the +ncexpand option ncverilog +ncexpand ...
4. Signalscan keeps busses vectored, so use any of the above options
instead.
The activity for busses are then derived correctly by pwrAnalysis. This is
what Rob needed. We have contacted Rob and the above suggestions worked.
Based on Rob's request to keep busses vectored during power analysis, we are
happy to say that this capability has been completed and will be introduced
in the next release of pwrAnalysis.
If other pwrAnalysis users are looking at implementing similar flows, I
hope this note can help them as well.
- Ankur Gupta
Cadence San Jose, CA
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