( ESNUG 397 Item 4 ) --------------------------------------------- [07/24/02]
Subject: ( ESNUG 393 #3 ) Two Users Pissed w/ Synplicity Docs & Design Flow
> Editor's Note: I want to thank Juergen for setting the record straight
> here. In my book, it's NOT a benchmark when the Synplicity people
> run the tool and report back their "results". This is not an anti-
> Synplicity sentiment. I distrust *any* benchmark data that comes from
> *any* EDA vendor. I've been lied to too many times. - John
From: Kevin Beasley <kbeasley@paradyne.com>
Hi, John,
I saw on Synplicity's website a response they made to some comments you made
regarding their tool. I wish you would 'rip them a new one' for their lousy
documentation, regarding the modular design flow for Xilinx FPGA's.
- Kevin Beasley
Paradyne Networks, Inc.
---- ---- ---- ---- ---- ---- ----
From: Alex Perry <alex.perry@qm.com>
John,
You don't want to know just how crappy Synplify is. Of course, it could
just be operator error, but I was having to do *more* manual optimization
than when I was writing brute force RTL equations directly. And the post-
placement timing-limited throughput was still 50% slower.
- Alex Perry
Quantum Magnetics, Inc. San Diego, CA
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