( ESNUG 398 Item 5 ) --------------------------------------------- [07/31/02]
From: Lydia Lee <llee@esilicon.com>
Subject: I Found Different Verilog Read Interpretations With DC 2001.08-SP2
Hi John,
I have a huge netlist, so I used "read_file -f verilog -netlist" to read in
dc_shell-t. I used DC 2001.08, 2001.08-SP1 without any problems. I just
switched to DC 2001.08-SP2 recently, and found an undocument feature/bug.
module top (...
inst_A U100 ( .delayout({aout, bout[1], bout[0],
cout[12], cout[11], cout[10], cout[9], cout[8]}), ...
inst_A U101 ( .delayout({dout[15:8]), ...
endmodule
With DC 2001.08-SP2, I ran the following 2 experiments.
Experiment 1:
read_verilog test.v
current_design top
link
all_connected U100/delayout[7] which gives "aout" - correct
all_connected U101/delayout[7] which gives "dout[15]" - correct
Experiment 2:
read_file -f verilog -netlist test.v
current_design top
link
all_connected U100/delayout[7] -> "cout[8]" - incorrect should be aout
all_connected U101/delayout[7] -> "dout[15]" - correct
I used the same netlist, same commands on DC 2001.08, 2001.08-SP1 with their
64-bit, Linux and SparcOS5 version. All of them give me correct result with
their netlist reader "read_file -f verilog -netlist". Only DC 2001.08-SP2
gives me incorrect behaviour. Please warn your readers about that. I filed
a support call to Synopsys as well.
- Lydia Lee
eSilicon, Inc.
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