( BSNUG 00 Item 7 ) ------------------------------------------- [ 10/13/00 ]
Subject: Altera, Xilinx, FPGA Express, FPGA Compiler II, Synplicity
THE SHAME OF BEING EDA: The laughing buzz overheard at the Boston SNUG in
the FPGA world was how Synplicity was IPOing itself not as an EDA vendor,
but as an 'Internet infrastructure provider' and how this opened them up to
possible future securities fraud allegations. On the technical side, Al
Czamara of ASIC Alliance warned designers about not fully testing their
FPGA designs and another set of presentations discussed block level
incremental synthesis in FPGA Express/FPGA Compiler II.
"I think it is a joke that some companies are hiding behind their
thumbs saying 'we are not an EDA company, we are an Internet
infrastructure provider'"
- Lucio Lanza, general partner at U.S. Venture Partners
(EE Times, 10/9/2000)
"Re-programmability is *not* a license to ignore verification -- don't
fall into that trap. There is little distinction between FPGAs and
ASICs when it comes to verification requirements."
- Al Czamara of ASIC Alliance Corp.
"I own FPGA Express and Synplify seats. The easiest way to explain?
They each do well what they each do well. My gripe? It'd be nice if
they both understood what "reproducable across versions" means. That
is, a new version usually gives new results - not usually better."
- Mark Garber of Equipe Corp.
"5) Programmable Logic Synthesis.
This session was composed of two:
1) Block level incremental synthesis run are now doable in FPGA
Express/FPGA Compiler II. This is available since version 3.4.
Blocks of the design have to be defined by the user as "block
roots" and they will be re-synthesized only if changes occur
in the source (relies on timestamps).
This improves synthesis runtime and palce and route runtime.
Examples showed 42% reduction in runtime for ~8500 logic cells
(didn't show how big was the change.)
A feature that is good to know now exists.
2) A flow for integrating PrimeTime with Altera FPGA. This flow
could be seen in the presentation I have or the SNUG web-site
(soon). This allows ASIC designer to continue with their regular
flow. The disadvantage of this is that SDF file Altera outputs
can only be used to perform worst-case (setup violations) analysis
in PrimeTime (best-case SDF is being worked on these days and
will be added soon).
The same capability, and same disadvantage, is used also by Xilinx."
- an anon engineer
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