( BSNUG 00 Item 9 ) ------------------------------------------- [ 10/13/00 ]
Subject: PrimeTime Static Timing Analysis (STA)
A WALL STREET LOVE AFAIR: I've gotten used to the Wall Street Analysts
calling me for explainations of EDA. (There are about a dozen of them
active and collectively they call about me 5 times per month on something.)
Usually it's about some controversial EDA issue du jour like licensing or
Physical Synthesis, with an emphasis on the money side. Recently, one of
them called and we somehow stumbled onto static timing analysis tools.
When I said "you probably aren't interested in that because it's almost a
Synopsys monopoly", I was quickly corrected with: "No! Monopolies are
good, John. They're guaranteed cash flow. Tell me more about this
'PrimeTime' software. What does it do?" (Dataquest's 1998 market share
numbers gave Synopsys PrimeTime 74.1 percent, Cadence Pearl 22.6 percent,
and Mentor SST Velocity 2.7 percent. That was 1998. My gut says it has
gone to even more PrimeTime in the upcoming 1999 Dataquest numbers due out
this month.)
"I found the PrimeTime tutorial to be very informative. I don't have
much experience with STA, and this tutorial helped to bridge the gaps
in my understanding of STA. What I especially appreciated was the
explanation of STA from first principles, at the transistor level."
- an anon engineer
"I thought most of the user presentations and tutorials were good.
The one on Primetime was good tho I didn't learn a whole lot of new
things. It was useful to hear about the bug on the "set_clock_latency"
command and I liked hearing the explanation of how the tool acts when
you use the "set_clock_latency" command as opposed to creating a
clock and moving out the edges with the "-waveform" switch."
- Tamar Barry of Honeywell
"Advanced Static Timing Analysis in Design Compiler and PrimeTime
Unfortunately, I was fooled by the word "Advanced" in the title of this
presentation. It was a good intro to static timing, but I did pick up
a few nuggets.
o 2000.05 has a new report_timing switch, -path full_clock.
This switch will include the buffers in the clock tree,
instead of just total propagated clock time.
o The create_generated_clock command is now in DC 2000.05.
This is great for divided clocks, and eliminates the need for
two-pass STA to determine correct insertion delays before
netlist level optimization with propagated clocks.
o There is a set_min_pulse_width command in DC2000.05
o There is a new algorithm in PrimeTime 2000.05 for calculating
transition times with back annotated net parasitics.
"In the past I've been reluctant to use any PrimeTime specific features
because I have to optimize in DC. I'm happy to say the feature gap
between PrimeTime and DC is closing nicely."
- Bob Wiegand of NxtWave
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