( BSNUG 00 Item 11 ) ------------------------------------------ [ 10/13/00 ]
Subject: Design Compiler 2000, Presto, Floorplan Manager, ACS
THANK YOU, AMBIT!: Even though the press gives more emphasis to C/C++ HW
design and physical synthesis, as a Synopsys user I've been over-joyed with
Cadence's Ambit-RTL synthesis. Yup, you read that right. I said "Cadence's
Ambit-RTL". Why? Because even though Ambit-RTL isn't used by anyone other
than Philips and a few independent consultants who can't afford to buy a
Synopsys DC license, the mere threat of Cadence Ambit-RTL has pushed
Synopsys R&D into beefing up DC 2000 with all sorts of new bells and
whistles! Customers always win when there's some good olde competition
keeping the EDA vendors honest. DC just keeps getting better because of
this. Thank you, Ambit-RTL, for improving Design Compiler.
"The Design Compiler 2000 Tutorial (FB1) featured a real live Synopsys
R&D manager! Jay Adams discussed his team's product, the Presto
parser. Although the Corporate AE's usually do a fine job presenting
these tutorials, the presence of an R&D person greatly enhanced the
presentation and resulting Q&A. We should encourage this level of
involvement in future Boston SNUG tutorials."
- Keith Silva of IBM
"The synthesis discussions were very interesting. I will be interested
in trying the Presto compiler and comparing the results to the
current default HDL compiler. The new "sticky" load command
(set_rtl_load) and generated clocks command will be useful. When I
get back to a register-based design, I'm interested in trying
behavioral retiming."
- Tamar Barry of Honeywell
"Logic Synthesis Improvements in DC 2000
This was the session to go to for all the gearhead details of DC2000.05.
Here's some of the good stuff:
o New HDL compiler (Presto), enabled by a hidden switch, will be the
default in 2000.11. They claim 6x average runtime improvement and
35% less memory used than 1999.10. It supports Verilog 2000
'generate' statements, shows state machine constructs on elaboration,
supports defparam, array instantiation, allows resource sharing with
Verilog conditional operator (but still won't guarantee a MUX!), can
infer MUXes from if statements with some unspecified switch or
variable. There was a claim of 5% area improvement using Presto.
o New Verilog netlist reader enabled by enable_verilog_netlist_reader
along with read -format verilog -netlist claims 3x memory reduction
and 3x average runtime improvement.
o ACS now uses RTL budgeting to eliminate the pass 0 compile. The
partitioning, directory structure, compile scripts and ACS commands
themselves are now user customizable.
o New commands set_input_parasitics, set_rtl_load to override wireload
models for known long nets.
o New command calculate_rtl_load to derive set_rtl_load values using
set_load and SDF from trial layout. Use for top level and RAM
connectivity nets.
o The set_clock_latency command adds -early and -late switches for
-source.
o Generated clocks now in DC!
o The report_timing command adds -path full_clock to show clock tree
drivers, -net -capacitance to show capacitance of nets. It also adds
-sort_by switch to sort by group or slack. Slack sorting is by
absolute value, ignoring any path group weighting values.
o Implicit dont_touch cells are now implicit size_only.
o Area optimization improvements yield 3-5% area improvement (average)
with some cases up to 20% using medium effort compile. Some designs
saw 0-5% increase but improved delay.
o Module Compiler's datapath synthesis is now used by DesignWare
Foundation, claiming up to 2x faster runtime, 12% better delay, and
10% better area. Adding an Ultra license gives the capability of
replacing transform_csa with partition_dp to enable Module Compiler
datapath partitioning of vector sums and sum-of-products.
o Min delay improvements include faster runtime on hold fixing, ability
to prioritize cell count over area, and multiple cell support for
set_prefer -min.
o BRT (Behavioral retiming w/Ultra license) now supports asynchronous
set/clear synchronous set/clear and load enabled flops without
decomposing.
o Floorplan Manager (part of DC Ultra) improvements include the ability
to specify pin and port locations for RAMs and macros, and
improvements to buffering and hold fixing.
Finally, here's a list of stuff on the horizon for DC:
o 64 bit
o VHDL Presto
o QOR improvements for simple compile mode
o RTL budgeting in simple compile mode
o HLO (High Level Optimization) speed up w/ lots of operators present
o Clock gating check like PrimeTime
o Case analysis like PrimeTime (won't remove logic!)
o Improved balance_buffer for non-skew controlled high fanout nets
o Automatic ungrouping of hierarchies
o Floorplan Manager support for overlapping obstructions, routing
obstructions, and reoptomize_design -top
o ACS supporting autopartitioning and acs_read_hdl
I also found out that the ideal_net attribute was supposed to be
enhanced to eliminate max_transition in addition to max_fanout and
max_capacitance. I was VERY disappointed to find out that it got
killed before beta. The lack of max_transition causes major grief when
trying to leave scan enables and resets for CTS. I have posted on
ESNUG about this in the past. I have some creative workarounds for
this, but I would really like to see the problem fixed in the tool."
- Bob Wiegand of NxtWave
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