( BSNUG 00 Item 12 ) ------------------------------------------ [ 10/13/00 ]
Subject: Automatic Chip Synthesis (ACS)
THE PATH OF LEAST RESISTANCE: Anticipating that RTL synthesis is going to
take a back seat to Physical Synthesis, Synopsys R&D has been working on
automating your typical RTL synthesis flow. Whether it gets better results
and whether customers will "take" to ACS is another matter altogether.
"6) Automatic Chip Synthesis (ACS) in Design Compiler
ACS is included in the Design Compiler and enables an automatic chip
synthesis. When doing bottom-up synthesis, constraint file for each
module needs to be provided, which is usually a hard mission. When
doing top-down synthesis, a top-level constraint file only is needed
but this does not work well for designs more than ~100Kgates. ACS is
the combination of both. It is part of the DC and needs only a
top-level constraint file. It reads in the RTL files and the top-level
constraint file and generates synthesis scripts and constraints for
each module (or heirarchy of modules). The timing and electrical
constraints for each block is generated by using design budgeting. The
ACS also outpts a makefile that is used for the rest of the synthesis.
After having a constraint file for each block, the ACS automatically
runs the makefile which compiles each block in parallel.
Advantages:
1) Automatically compiles blocks in parallel.
2) Needs only a top-level constraint file.
3) The constaraint files could be evaluated and changed if needed.
4) Generates an automatic makefile.
5) After the results are analyzed, if they are not good the ACS could
be run again ( acs_recompile_design command ) or if they are
partially good the commands acs_refine_design could be used.
Disadvantages:
1) When compiles in parallel, uses several licences in parallel.
2) Accurate constraints?
ACS seems like a nice thing to try out. The presenters where from R&D
and could be addressed with questions about this. If not for accuracy
issues, ACS could be used for writing initial constraint file for
reference and generating the makefile."
- an anon engineer
"Synthesis and Coding Techniques
A presentation from DSP Group described the use of ACS (Automated Chip
Synthesis) on their DSP cores. It was pointed out that top down
ACS synthesis did not give the best results on a 300K gate DSP core.
Cliff Cummings presented a paper about designing FSM's with glitch-free
outputs using one hot encoding. Good paper.
Tensilica did and interesting presentation about power optimization
with their cores. Their techniques include reducing gate count by
selective implementation of features, clock gating, and performance
trade-offs. Their tools provide a graphical tradeoff analysis of
power, speed, and size. They presented some interesting data
comparing compile strategies, and showed their best QOR (Quality Of
Results) came from a combined bottom up/top down multi-pass strategy
(which is what I do). They particularly pointed out that top down
ACS gave inconsistent results, huge runtimes, and sometimes didn't
finish on 40K-50K gates."
- Bob Wiegand of NxtWave
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