( BSNUG 00 Item 14 ) ------------------------------------------ [ 10/13/00 ]
Subject: Power Compiler, Prime Power, Module Compiler
ANOTHER MONOPOLY: The other little monopoly that most Wall Street weenies
don't know Synopsys has is in power optimization. Yes, -- Sente, Cadence,
Avanti, Simplex, and Mentor all offer some sort of power analysis set of
tools; but Synopsys is the only EDA company that offers users a tool that
actually does something about cleaning up your power problems. Of course,
the moment you even say the words "gated clocks", you've immediately made
yourself the lifetime enemy of the engineer on your team who's responsible
for the scan testing of your chip, but at least it's low power! On the
flip side, Module Compiler got only a moderate notice (because datapath
design is a specialized type of designer) and nobody mentioned Behavioral
Compiler in their reviews of this SNUG.
"TB1 - Module Compiler, Design Power 3 stars (out of 3)
How to design for lower power consumption was the focus of this
presentation. This session picked up on one of the themes of the week
that low power design is becoming more of a critical issue. It was
targeted at the Actel ProASIC FPGA library, but most of the information
is easily applied to any standard cell flow. The author suggested that
for optimal results, low power should be considered at each level of
abstraction of a design, i.e, 1) pick power friendly datapath elements
2) use power driven synthesis 3) power driven floor planning and
4) chip level power verification. Most of the presentation, however,
dealt with optimal selection of data path elements and their synthesis.
Major concepts were: power consumption is switching activity dependent:
so strive for a datapath with fewest nets switching; consider
pipelining to reduce length of datapath combinatorial runs; turn off
portions of a datapath when not in use; reduce fanout if possible via
selection of data path components. The author characterized quite a
few test cases based upon adder and multiplier circuits to verify his
suggestions."
- Brian Fall of Microchip Technology, Inc.
"Power Compiler
--------------
This tool uses 3 techniques to reduce power.
1) Inserts Clock Gating:
This will allow the clk input of a register to switch only when it is
necessary. The recommended technique includes adding a negative
enabled latch and an AND gate into the path before certain registers.
Alternative methods such as a single AND gate or OR gate are bad
techniques because they can result in glitches.
2) Automatic Operand Insertion:
This technique involves re-arranging combinational logic to keep it
from "rippling" through a result when it is not needed. An example was
given with 3 MUXes in series. Each of the 3 MUXes has an independent
select line. Power Compiler would change the design to insert AND
gates before the first MUX data inputs. The data would pass through
the AND gates only IF both the second and third MUX are selected. This
would reduce data switching through the first MUX. Naturally,
depending on the width of the data path, a good number of gates will
be added to the design.
3) Gate Level Optimization:
Techniques at the gate level like: Sizing, Tech mapping, Pin swapping,
factoring, buffer insertion and Phase assignment. Not all were covered
in the presentation. The ones I caught were:
- Tech Mapping: hiding high toggle rate nets inside cells. For
example an AND gate with a high toggle rate output feeding an
OR gate would be combined into an AND-OR gate.
- Factoring: reduce network toggling by moving a high activity net
farther down a combinational cone of logic towards the result.
This reduces the number of gates connected to the high toggle
rate net.
Simulation:
Power Compiler can collect switching activity from SAIF (Switching
Activity InterFace) files generated by monitoring your simulations.
These SAIF files guide Power Compiler as to where to reduce power in
your design. The SAIF files can be extracted through the Verilog PLI,
Modelsim MTI (DPFLI) or a VCD conversion. Multiple SAIF files can be
merged together before feeding them to Power Compiler.
Prime Power
------------
Prime Power is a separate power analysis tool. It can be used to view
power consumption "hot spots" graphically or through reports. It is a
more comprehensive tool than the DesignPower analysis tool that comes
with Power Compiler. The GUI interface looks like an Oscilloscope
screen showing power consumption at key nets over time. Prime Power
take in 3 input files:
- PIF file: includes switching info on each net from gate simulation.
Different from SAIF.
- Wire Cap file
- Synopsys .db file. Includes library and power info.
Prime Power works at the gate level as opposed to another tool called
PowerMill which looks at power consumption at the transistor level.
Random Notes:
- The worst case power data will be extracted running at best case
simulation conditions (P,V,T) Switching rates will be fastest then.
- PowerArc tool can be used to generate a library with power info to
allow you to run Power Compiler and Prime Power.
- The instructors say some vendors are pushing towards doing "power
signoff" in the future.
- Clock skew is always an issue when logic is inserted into the clock
path. Supposedly, most vendor clock tree insertion & optimization
tools can handle this.
- To get accurate power toggle info, your simulations need to reflect
what you will do in the real world. Garbage In = Garbage Out
- It seems to me that Power compiler may add a significant number of
gates to your design if not controlled. You could have problems
if you have to bump up a die size, or get timing problems as a
result of using it.
- Cost of these tools: Power Compiler: $90K, Prime Power $80K for a
permanent Synopsys license. Probably 15% maintenance. The price
should be 1/3 of permanent numbers for yearly "lease."
The presentation slides could have been more organized. I felt that
the flow wasn't clear and I had to piece it together. However, the
presenters were very enthusiastic about the products. I believe they
were both Power AE's.
These tools seem like a must for anyone doing low power designs such
as cell phones, PDAs or other portable electronics... assuming that
your volumes will be high enough to justify the high purchase price."
- Ira Hart of Galt Design
"What I took away from Boston SNUG is Prime Power and Power Compiler.
I don't know if it was because they are ready or we are ready. Mobile
wireless communications equals the hot stuff and they require low
power solutions. DSP is synchronous, scalable and synthesizable but
done the easiest Design Compiler way it is power hungry. Power
Compiler does what DC arguably should have done from the beginning:
gate the clocks instead of re-circulating back through a MUX. I
have suspicions this will help with timing as well. Is Power Compiler
going to help us meet our power goals? Is Prime Power going to help
us identify our power problems? We will let you know, John, if these
two tools help us with low power design."
- Martin Gravenstein of TDK Semiconductor Corp.
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