( DAC 00 Item 2 ) ---------------------------------------------- [ 7/13/00 ]
Subject: C-Level Design, Cynapps, CoWare, and Synopsys 'SystemC Compiler'
IF AT FIRST YOU DON'T SUCCEED: One of the loudest companies in the C/C++
foray last year was C-Level Design. They promised all sorts of great things
like using C/C++ as a behavioral level tool. Their attitude was "Verilog?
VHDL? RTL synthesis?... That's all OK for you chip designing infants.
The *real* systems designers operate at a truely Higher Level by designing
in behavioral C and using our System Compiler(tm) to make a chip!" The
funny thing about DAC claims is they only have a year to make it happen or
it's Egg On Their Face time. And C-Level has Omlette Level egg time now!
A few weeks before this year's DAC, I had a rather interesting conversation
with one of my readers who did a beta with System Compiler. Yes, C-Level's
System Compiler synthesized C into RTL Verilog, but the RTL Verilog wasn't
synthesizable to gates. That is, you couldn't make actual buildable chips
using this tool because it resulted in designs that had state machines with
thousands of states, nightmare datapaths, and hundred layer logic. This
output from System Compiler couldn't ever make timing ever and some of the
RTL constructs it spit out weren't synthesizable at all. In short, it was
a beta nightmare for C-Level.
When I saw them at DAC, I told them about that conversation, and, with much
integrity, they very quickly agreed it was true. They wanted to know if it
was Motorola in Fort Worth or Sony in the UK who told me first. "Last year
we used to talk to customers and we felt that they were snickering at us
when we left the room," said Kevin Hotaling of C-Level. "They knew more
about this problem than us. Now we know more than everyone because we've
done our time in the woods."
This year at DAC, C-Level punted the behavioral C and is refocusing on just
making structural ANSI C synthesizable to Verilog RTL. They claim that you
will still be able to use C's pointers, structs, arrays, unions, objects,
and classes -- but in a moderate way. Users seem to be OK with this, but,
as always, we're all waiting to hear when the first real chip is taped-out
using their tool and the nitty-gritty details it took to get there.
(Be sure to read the 'Behavioral Compiler' part of this report -- it has a
lot of related customer quotes on C/C++ synthesis there.)
"We have C Level Design tools. They work for us now, at least in trial.
We plan to use their tools in an up coming project. We have looked at
many other vendors. In our opinion, C Level Design is that best
available today, but Synopsys will be the best once their tools have the
features we need (by the end of 2000 it looks like). We plan to move to
Synopsys tools when they are ready. I expect it will take 3 to 5 years
before we move from a VHDL flow to a C flow because it will take that
long before all the required tools are available."
- an anon engineer
"C-Level Design
- I finally was explained how they handle concurrency, hierarchy and
time. They fake it by having all input/output to C functions be an
array with 2 locations: one for the input, one for the output. The
output value replaces the input value at the next clock cycle. That
way the order in which functions are called in irrelevant.
- Very intuitive to use at the RTL level but this cycle-based approach
limits the usability & portability at higher levels of abstractions.
My bet is you'll see a LOT of incompatible models written at that
level and the mess will still remain.
- The AE I spoke to eventually agreed that C was not that cool for
testbenches since it did not offer good concurrency & communication
control compared to Specman or Vera.
Their value-add is a yellow brick road between C models and RTL coding
in HDLs."
- Janick Bergeron of Qualis Design (VG 1.13)
"CynApps: Good idea, but they still have some serious issues to resolve
before it's all over. Biggest problem is that their C simulator and
their cynthesized Verilog simulation won't necessarily give you the same
answers if the underlying C++ code suffers from call-order problems.
Also, if you are trying to simulate a design, there's no good simulation
commands to (for example) step 100 cycles, or examine a particular RTL
signal at any level of abstraction. It is good for the stepwise
refinement idea, but isn't really all that friendly otherwise.
SystemC: Has concurrency problems as well. There was a lot of buzz
about SystemC before DAC, so I let others in my group hound the SystemC
guys while I looked at other vendors.
Interesting thing at DAC was that on Monday Cadence announced support
for SystemC, and on Wednesday announced support of CynApps. Playing
both sides of the fence might (or might not!) be the prudent thing to
do. I'll be very interested to see where this all goes."
- an anon engineer
"C-Level's tool could have a place in a design flow. Their ANSI C
compatibility is a plus over Synopsys's SystemC Compiler. The problem
is getting designers to work in C rather than Verilog/VHDL. At 95K per
license it looks pretty steep to my eyes. I don't know what Synopsys
is charging for their similar tool."
- an anon engineer
"Didn't look at C too much. But I don't believe C-Level's 1500x speedup
number. Cynapps admitted their simulation isn't much faster than
something like VCS; they just think everyone wants to design in C++."
- an anon engineer
"Co-Ware -
Their Jay Leno/Bill Gates skit was pretty funny, but their Napkin to
Chip concept was pretty much a repeat of last year's demo from what I
could tell. Their claim is that their tool provides a higher-level
concept visualization and helps the software/hardware partitioning.
It can also output interface code and interface RTL for synthesis."
- an anon engineer
"C-Level
This company provides a C to Verilog or VHDL converter. We could use
this tool for testing the [ design deleted ]. We currently do not have
the ability to test every case for the [ design ]. We have in the past
modeled the [ design ] in C and done some testing. However the VHDL
that was written could be different than what is modeled in C. C
modeling and testing is easier and faster. The C-Level conversion tool
offers ANSI C / C++ compatibility. We could slowly use this tool for
more and more design blocks. Some designers might prefer to write there
code in C. Port drivers could also be done in C. The conversion tool
provides a fully synthesizeable Verilog or VHDL file. So we could use
this as an extra part of our simulation environment. C-Level has
experience with five million gate designs and compile times of
approximately 1 million gates per 2 hours. The software runs on either
NT or Solaris with signal name retention assured. All compiling,
debugging and testing could be done on PC's. A possible drawback is the
cost of the license, approximately $95 K. We would have a hard time
keeping this license busy. License is only for the conversion step."
- an anon engineer
"C Language Simulation/Synthesis
This is an area that was hot last year - a number of companies were
pushing describing your ASIC in a subset of either C or C++, simulating
it there (which is faster than an RTL) and then automatically
synthesizing your RTL from C/C++.
The new SystemC standard that Synopsys is pushing is having its effect
on the established players in this market. Most of the sales pitches
talked about either how similar they were to SystemC or how their flavor
of C or C++ was superior to SystemC.
C-level Design sells a tool that accepts C and outputs RTL. They say
they now recommend using "cycle C" - C with clock cycles in it
explicitly. This is something that editorials have been commenting on
- if you tweak C enough that you can model concurrency and the passage
of time, eventually you just get another RTL, so what's the point in
using C? They say that unlike Cynapps they can simulate with any
standard C/C++ compiler.
Cynapps accepts C++ and outputs RTL code. They say they are superior
to C level because they are at a higher level. Their C++ is similar to
SystemC but they say it is more extensible.
CoWare's N2C tool also translates C into VHDL or Verilog, but claims to
do a lot more. It is aimed at system partitioning and hardware/software
codesign. The designer creates an initial untimed C model of the
system. This is then refined into a cycle accurate model, which is then
implemented in HDL. It is also supposed to make IP use easier. Don't
know if it's really different from the tools above or just marketed
better.
Frontier Design sells tools that sound awfully similar to C-Level."
- an anon engineer
"Most of the C-level tools are still stuck at the RTL or cycle-based
level. What we need is a solution that has the ability to handle
different simulation and design domains, such as synchronous dataflow,
asynchronous dataflow, analog, gate level, cycle based, RF, etc.
The reason why many companies are using C for system level verification
is the speed, cause you can be more than 100 times faster than with an
event driven HDL simulation. The language or tool must give you the
ability to refine your design starting from the system level without
timing information down to a RTL represemtation.
I think CoCentric SystemC Compiler is a step in the right direction."
- an anon engineer
"CoWare:
These guys had a cheezie yet funny skit with a Jay Leno and Bill Gates
look alikes. Was pretty good for a geek show. N2C or napkin to chip
is their tool. Lets you enter C for everything and then play HW/SW
arch trade offs. The hardware then can be translated to RTL. Very
SystemC-ish they say. Still could not get much info with the time I
had. I think they define a C style that can be mapped into an HDL. I
think they support SystemC in that they can hook up to the SystemC
library parts.
C Level:
These guys have a C to Verilog translator. It can be run standalone on
a C compiler based simulator that can even spit out standard dump files
to compare. Their C style has to be learned. Only their C styled code
works for translation to HDL. Not really addressing a C standard for
verification, just use C anyway you want for verif."
- Peet James of Qualis
"CoWare partner demo with IKOS's new emulator was pretty impressive.
A cell phone design, processing conversation (speech samples) right
there on the DAC floor -- now that is what good DAC floor demos are
made of! Of course 'smoke and mirrors' and attractive spokesbimbos
are also what DAC floor demos are made of as well. :-)"
- an EDA salesman
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