( DAC 00 Item 13 ) --------------------------------------------- [ 7/13/00 ]
Subject: Cadence 'Verification Cockpit'
A LITTLE HIGHER: Not quite a Verilog/VHDL tool and not quite a pure play
C/C++ tool, Cadence again showed their Verification Cockpit tool at this
year's DAC to high reviews.
"Cadence 3 stars (out of 3 possible)
Verification Cockpit
The Verification Cockpit was first announced just over a year ago. But
with the latest enhancements and the bundling of the tools, I think
Cadence has put together a good story for the verification engineer.
The Cockpit integrates the Signalscan Transaction tools which provide a
higher level of abstraction for bus or protocol transactions, a code
coverage tool, a "lint" tool for RTL purification, and a new tool called
TestBuilder which allows a verification engineer to bind C/C++ testbench
code into the verification environment. TestBuilder supports C++
libraries which have been generated to support the four logic states
for boolean logic. A number of special constructs such as smart queues,
queues, semaphores, and other high-level constructs are also supported.
In addition, another tool called TxE provides so-called functional
coverage metrics which allows the designer to specify certain test
parameters which are monitored during the simulation run and reported as
pass/fail at the end. Some of the GUI reporting methods are a bit of
fluff and can create "manager-ware" charts, but the TxE tools does in my
opinion provide some value to the verification engineer.
Compared to Synopsys' VCS plans, I think the Cadence tool has a bit
better overall infrastructure with the transaction capability and the
built-in "smart" data structures. However, I think the VCS approach for
adding C/C++ code to the simulation environment is a little better than
what Cadence has done with TestBuilder. TestBuilder and the transaction
stuff is currently only supported using the NC-Verilog similator which
is a drawback."
- an anon engineer
"I saw the demo for Cadence's Verification cockpit. It's a combination
of a code coverage tool, a linter, a transaction viewer, a testbench
authoring tool and a "functional coverage" tool. The code coverage
tool is line coverage only - pretty rudimentary. The linter is
currently Verilog only. It is programmable and comes with synthesis
and Reuse Methodology Manual rules. The test bench authoring tool is
currently Verilog only and takes C++ as input. It uses transactors and
C++ code to drive your simulation. The assumption is that a low level
hardware guy enters the transactor data then some high level system guy
enters the C++. The "transaction explorer" displays errors at a higher
level than ones and zeros. For example, it will say where within a
packet an error occurred. The functional coverage tool attempts to tell
you which input to output paths were exercised. If input creation and
output testing were called within the same C++ function, it associates
the two and says that path was tested when that function is used. These
tools are all extra buttons on the existing Simvision GUI."
- an anon engineer
"TestBuilder, a C++ based testbench library within the Cadence
Verification Cockpit, lets users develop hardware testbenches. Cynlib
is a C++ class library, facilitating hardware description directly in
C++. With TestBuilder and Cynlib, you can design and verify the design
in C++. You can then synthesize the design's HDL representation using
CynApps' Cynthesizer for RTL synthesis by standard design tools."
- Jim Lipman of TechOnLine
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