( DAC 00 Item 19 ) --------------------------------------------- [ 7/13/00 ]
Subject: Linters -- TransEDA, Avanti Novas, DualSoft, Veritools
LINT IN MY BELLY BUTTON: Last year there were something like 13 different
lint-like tools for Verilog and VHDL source code on the EDA market. The
big controversy then was that Avanti bought interHDL (which had Verilint),
renamed Verilint to Nova and jacked up the $8 K price to $47 K. Caused a
small customer rebellion and inspired a number of lint competitors...
"Avanti's Novas: Not bad - good combination of useful tools if you have
the budget."
- an anon engineer
"BTW, Novas Software has nLint, which is different from Avanti's
Nova-Explore."
- an anon engineer
"DualSoft offered two cheap linters, ReviewVHDL and SuperLint."
- an anon engineer
"Lots of lint-based tools. Not much in the way of real coverage, though.
If I want to know that all PCI system requests have been ACKd, or that
all arcs of my state machine have been covered, there still aren't any
EDA tools out there that can adequately address the problem. TransEDA
was the best bet in this category, though. I think they are farther
along in the areas of coverage and general environment."
- an anon engineer
"I believe we will move into some sort of static HDL checking in the
future via lint. I am not sure which one looks good, but in New
Orleans we were looking at the LEDA's lint, which was sucked up by
Synopsys last year. Guess will have to look at this again when we have
more time.
We currently own TransEDA VHDL Cover. Their new Verification Navigator
was a HUGE improvement over VHDL Cover in terms of ease of use."
- an anon engineer
"I have a nomination for worst DAC giveaway. The so-called "Verification
Methodology Manual" book from TransEDA. I sat through a demo to get
this piece of shit. I read it on the flight home and it is the one of
the most obnoxious and blatant product plugs I have ever seen. They
don't even begin to cover a decent "verification methodology." As far
as they're concerned, all you need is code coverage. I'm sure that all
the other vendors selling verification wares besides coverage tools
agree! Forget testbench generators! Forget lint! Forget equivalency
checking! Forget emulation! All you need is code coverage, and all you
need for code coverage is VN-Cover from TransEDA. Granted, VN-Cover
looks like a decent tool, but they had to write a book to sell it? I
was actually offended that this book has a cover price of $64 and that
somebody might actually waste their cash on this worthless load of
trash. Even if it was free to everyone, it still isn't worth it. They
need to find a way to replace to two hours you spent reading it."
- an anon engineer
"As for the Design Rules Checkers (DRCs), aka linters on steroids, like
ProVerilog from Synopsys and VN-Check from TransEDA, I like the idea,
and they both have nice GUIs, especially VN-Check. My problem here is
that I can't get half my designers to even run lint (we went from
Verilint to Surelint last year), so I don't see these tools taking hold
here."
- an anon engineer
"Two experienced VHDL users in my EDA class wrote a tool a lot like
Veritool's HDL-Lint. Just like C Lint, these tools are very useful,
but they are primitive compared to those available for regular
programming languages. But it certainly is an area where a good tool
could really save a designer a lot of time & avoid design iterations."
- Hank Walker of Texas A&M University
"Sorry, isn't EASE a graphical entry tool? We were supposed to use it
but soon thrown it out of our flow. We had also TransEDA VHDLcover
which has now increased to the 'verification navigator (VN)'. Looks
good and I intend to have a closer look. Other's I don't know really.
Big problem for us is once more the fact that we are using VHDL."
- an anon engineer
"Code coverage: I only had time to look at TransEDA - it is suposed to
have the most bells and whistles and is the most popular. SureCove is
suposed to be the fastest.
Linters: Saw the regular ones that have been out for awhile and these
new ones:
A) Dualsoft Review HDL - Verilog and VHDL - need rules. Right
rules in Java.
B) TransEDA VN Check - Verilog and VHDL - need rules.
The common need on all the linters is the actual rules. They all have
the means to add rules, and check rules , and turn rules on and off, but
they need help with actually making and entering the rules."
- Peet James of Qualis
"Most people hate coverage because it is just such a pain to do. The
reason it's such a pain is that the automatic instrumentation identifies
so many don't cares and not enough really interesting conditions.
Reviewing coverage reports involves sifting through the don't cares, and
a form of code inspection to figure out what the line does that is not
covered. This can be quite painful - especially if the person reviewing
the coverage file is not the designer.
I'm really starting to think that going back to a manual insertion of
the things you want covered (preferably during the design process)
results in the best bang for your buck."
- Dan Joyce of Compaq
"Interra also makes a linter that does both VHDL and Verilog. They felt
that Leda is pro-VHDL and Avanti is pro-Verilog. Their linter also
various types of checks, like whether the code is synthsizeable, whether
it violates any testability rules, whether it complies with the Reuse
Methodology Manual, etc. You can program your own rules in Perl."
- an anon engineer
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