( DAC 00 Item 21 ) --------------------------------------------- [ 7/13/00 ]
Subject: Denali Memory Models & C
"ME, TOO!, ME, TOO!": Along with all the other functional test tools going
into the assertion checker business, memory wrapper vendor Denali is also
jumping into that methodology with both feet.
"Denali, which sells C language memory models, is going into the IP
business. They sell Verilog memory controller IP."
- an anon engineer
"Denali 2 stars (out of 3 possible)
Memory Modeler
Denali's memory modeler is a very useful tool for generating simulation
models of various types of memory's for system & chip-level simulation.
The tool is used to model memory components in C, Verilog, or VHDL. The
specific behavior and key parameters of the memory to be modeled are
defined within a proprietary format called SOMA. From the SOMA spec,
the Memory Modeler tool outputs an HDL source file to be used as a shell
for instantiating the memory within the testbench/RTL. This shell calls
a C-language object during the simulation which is also generated. Such
an approach using a C API to the logic simulator would fit well into a
C-based verification methodology. SOMA files can be obtained from many
memory manufacturers or from Denali and include support for DDR-SDRAM,
SGRAM, SDRAM, EDO-DRAM, RAMBUS, FLASH, SSRAM, RDRAM, FIFO's, and various
types of PROM/EEPROM. Denali customers also have free access to the
http://www.eMemory.com design portal where users can search for memory
parts and other information.
Denali has now joined the stampede of vendors rushing to join the
assertion checker club with their PureData product which allows a user
to set breakpoints and check assertions for certain types of memory
accesses such as memory leaks, redundant reads, etc. But some useful
higher level functions also supported are the ability to manipulate
linked-list pointers, flatten complex interleaving schemes, and
interactive memory content viewing and transaction analysis."
- an anon engineer
"Denali sells C language memory models. The models have configurable
checks and supposedly some clever scheme to use as little actual memory
on your CPU as possible (important if you're modeling, say, a memory
board). They can be hooked into most VHDL or Verilog simulators. James
Lee of Intrinsix, who has written two Verilog books, noted that their
models also had some built-in assertion checks like 0-in. He theorized
that checks like this (for example, declaring an error if you overwrite
data without ever reading it) might one day be standard, just like setup
and hold checks, which were not originally part of Verilog. In the past
year they've added even more sophisticated checks, like checking linked
lists resident in memory."
- an anon engineer
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