( DAC 00 Item 26 ) --------------------------------------------- [ 7/13/00 ]
Subject: Sequence WattWatcher, Synopsys PrimePower, Summus PowerEscort
POWER TWEAKING: One of the most interesting predictions I saw at DAC was by
Dataquest concerning the Cell Phone market. They said that the year 2000
sales for Cell Phone chipsets would come to an estimated $7.7 billion. In
four years (2004), that would grow to $22.6 billion! That's almost 3X in
just 4 years! And it got me to thinking about the importance of EDA tools
used to estimate, analyze, and reduce power in designs. The funny thing was
that everyone wrote about power analysis tools yet there was very little
mention of power reduction tools like the Synopsys 'Power Compiler'. Why?
Do power problems just magically fix themselves as long as you find them???
"Sequence Design 3 stars (out of 3 possible)
WattWatcher/WattSmith
Sequence is a new company formed from the merger of Sente & Frequency.
They emphasize power and signal integrity tools. The Sente tool suite
has been available for some time in the CAD tree. I saw an update of
the WattWatcher tool which provides an RTL and gate-level power analysis
capability. It uses simulation to measure signal toggle rates and
combines this with physical loading and library information to estimate
power. Sente now supports the standard OLA/ALF simulation library
formats which makes the tool easier to run with different vendors. The
GUI provides a color-based graphical analysis of the power dissipation.
In addition, the WattSmith tool provides the user with an analysis which
suggests ways to reduce power consumption and the quantitative effects
of implementing the suggestion. I do like this tool because estimating
power dissipation in a chip is a very imprecise science and there is a
lack of tools which provide some insight into this matter. The tool
seems fairly easy to use and setup and works with whatever simulator
that you require via the PLI interface."
- an anon engineer
"In power Epic, Veritools, Sente, TransEDA, Simplex, Iota and Summus
were all there again this year. Iota claims their RTL power analysis
is very close to final analysis after place & route.
At the reliability talk, the Simplex speaker said that most power grids
are over-designed because the designers don't know exactly what they
need, but when Simplex's tool is run on DSM designs, 75% still have
power/ground problems, 20% of which are fatal."
- an anon engineer
"There was push for 'liquid libraries' once again from Semantics, Moscape
(bought by Magma), etc. Their idea is to synthesize library cells on
the fly, as directed by synthesis. They claim improved speed and power.
Of course, it helps them make money by selling lots of copies of their
product by incorporating them in the design flow. In reality, most of
the gains may also be realized through resizing the transistors (a la
Telos) to lower power and some speed improvements. Claims of 15% to 20%
power savings were made, but using older larger height libraries. I
have some doubts about customer acceptance, because customers want to
simplify the design flow, not add more loops to it."
- an anon engineer
"Summus ( PowerEscort ) -- IRdrop, based on LEF/DEF, unprofessional
presentation, office only in Korea, NEC only major customer, not
convincing in terms of accuracy."
- an anon engineer
"Our foray into RTL power analysis happened a few years ago due to design
constraints on some of our larger chips. At the time, we were working
on a some very large ( > 1 Million gates ) IBM designs. These chips
were replicated many times over on boards, which themselves were
replicated over in large racks. System level cooling quickly became an
issue for us. We were doing power analysis using spread sheets, but
were wary of the results due to too many unknowns in the assumptions
that we were making for estimates in for activity and cell energy. Our
estimates put us right at the power limit, and any error would have put
us over the limit. Important early power/cooling decisions had to be
made. Quick synthesis to gates was not an option either, due to size of
the design. (Gate level simulations were far too large and slow to
provide us with the timely data to make important design decisions.)
We asked IBM for help and they suggested that we take a look at Sente's
WattWatcher.
We brought in WattWatcher and tried it on one of the largest chips in
the system. After getting past some initial idiosynchrosies from our
design practices, we were up and running and producing data. The
longest step in the process was running our simulations, which took four
to six hours to run per test bench, but we needed to run specific tests
to get the critical data that we needed. The power analysis only took
15 to 30 minutes to run per test bench. We eventually ran all the
designs in the system through WattWatcher. The results that we got back
showed that our spread sheets were in fact overly conservative and that
we had some head room in total system level power. Between the results
that we obtained in WattWatcher, and our initial spreadsheet estimates,
we made the judgement call that we would stay under the total power
limit for the design.
When we got silicon back and performed some measurements, the measured
power correlated nicely with WattWatcher and showed that our spread
sheets were in fact too conservative. The speed and capacity of
WattWatcher allowed us to do analysis that we were never able to do
before. We were able to implement a methodology were we could use
system simulation data that mimcked the entire operation of the whole
system, giving us analysis capabilities that provide more real life
estimates."
- an anon engineer
"PrimePower models pattern-dependent, capacitive switching, short-circuit
and static power consumption, considering instance-specific cell-state
dependencies, glitches, multiple loads and nonlinear ramp effects.
To use PrimePower, an engineer first runs an HDL simulator and generates
what Synopsys calls a PrimePower interface format (PIF) file. That
contains switching activity and hierarchy information. The file is
created by programming language interface routines provided with the
tool. PIF files can be generated by Synopsys' VCS Verilog, Cadence's
Verilog-XL and NC-Verilog and Model Technology's ModelSim VHDL
simulators.
PrimePower also requires ASIC libraries characterized for power in
Synopsys' ".db" format, which is accomplished with, but does not
necessarily require, Synopsys' PowerArc tool.
A third source of input is parasitic back-annotation data, which can be
a capacitance table or a detailed standard parasitic format file
generated by Synopsys' Arcadia product.
The largest design Synopsys has done had 1 million instances and ran in
about four hours on a 2-Gbyte workstation, Ruby said."
- Richard Goering of EE Times reporting on Synopsys PrimePower
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