( DAC 00 Item 35 ) --------------------------------------------- [ 7/13/00 ]
Subject: Mentor 'TeraPlace', Sapphire 'FormIT/NoiseIT/PowerIT', Incentia
AT LEAST MENTOR WAS CREDIBLE: Freshly exhausted from the run-around I found
checking out those so-called 16 Silicon Perspectives "tape-outs", the poor
marketing saps at Mentor got Total Hell from me when they called about
having seven tape-outs with their new TeraPlace tool. (I won't say what I
threatened if I found out they were lying to me, but within 2 hours I had
two customers independently confirming three tape-outs to me.) Cool. Means
that at least THIS tool is viable (at 0.25 & 0.18) as far as I'm concerned.
TeraPlace is a post-synthesis placement optimizer/re-optimizer that reads in
a Verilog netlist or LEF/DEF files along with Synopsys timing constraints
and/or extraction files from tools like xCalibre or Cadence HyperExtract.
(TeraPlace was developed at Mentor from the ClockCAD aquisition.) TeraPlace
works by moving gates, adding/removing buffers on nets, and resizing gates.
It does clock tree synthesis, ECO placements, and re-optimizes placement to
deal with congestion. Their claim to fame is TeraPlace can intelligently
balance congestion and timing issues simultaneously. With their extensive
extraction experience (from writing xCalibre), the Mentor R&D claimed that
TeraPlace worked with three distinct extraction modes. The first was that
it could use the simple wireload models generated by Design Compiler. The
second was a per-unit-length-capacitance mode (usually from placement and
IPO type synthesis.) The third, and most interesting, was what he called a
'coupling-based' mode where congested nets got more capacitance (from cross
coupling) than non-congested nets (as in from a full extractor!)
TeraPlace is a flat tool (as in it doesn't do hierarchical), but they claim
it can handle 4 million gates on a 32-bit UNIX workstation.
The way Mentor sells TeraPlace is as an 'insurance' tool. You don't have to
change your standard 'Synopsys DC to Cadence SE / Avanti Apollo II' flow.
Just use it in between DC and final routing. If it improves your design,
great! If it doesn't, don't buy the tool. A clean, painless marketing idea
if I say so myself. Synopsys PhysOpt is a bit like this because it appears
as just a few new added DC_shell commands to the user. In contrast, any of
the Magma/Monterey/PKS flows mean a very scary leap of faith into a totally
new design flow with all new, scary software. (We're talking serious 'Red
Badge of Courage' bravery there!)
"On request of Jeff Wilson of Mentor, I hereby affirm that we at
[ deleted ] did use TeraPlace on our [ deleted ] chip design and
[ 2nd deleted ] design. The [ deleted ] design is taped out and in the
stage of production. The [ 2nd design ] is now canceled due to business
change ([ company name ] is now owned by [ 2nd co. name ] from Taiwan).
Also [ deleted ] group at Austin is using TeraPlace and they taped out
the latest chip [ 3rd deleted] with TeraPlace as the placer."
- one of the two TeraPlace tape-out confirmation e-mails (after
I cleaned up all company identifiers )
"John, Jeff Wilson at Mentor asked us at [ deleted ] to give you some
info about our use of TeraPlace. I understand this info will be used in
a newsletter and that we'll remain anonymous.
As of 6/26/2000 [ deleted] has taped out one design using TeraPlace and
we continue to use TeraPlace in our production flow. Hope this helps!"
- the second "cleaned up" TeraPlace tape-out user letter
"Mentor - Teraplace - placer/PBO/CTS, offers plug-in replacement for
Cadence's Qpopt/Ctgen, claims to improves timing closure by better
handling timing inside the placement algorithm and by 2.5D extraction,
during optimisation."
an anon engineer
Another tool similar to TeraPlace was Sapphire. Sapphire 'FormIT' had a
customer tape-out story up on Goering's http://www.EEdesign.com website
about two months before DAC. I don't know much about Sapphire; they weren't
mentioned much by the users in my survey. I also found one standalone user
quote about another company called Incenia. I don't know about them either!
"* Sapphire: They seem to be getting their act together. Several
capabilities are operational now, including placement, global routing,
early signal integrity analysis based on placement & global routing,
several synthesis capabilities for timing correction. Things seem to
be well integrated. It is hard to say whether they can compete with
Magma/Monterey. However, their narrower focus may be their hope for
success."
- an anon engineer
"One of the new entrants in the physical synthesis race is Incentia.
Their tool is now in beta. They claim to be within 10% of the area and
size of Synopsys but run 5X to 10X faster.
Sapphire Design Automation sells formIt, another new physical synthesis
tool. It can take RTL, a netlist, or a placement, and produces a routed
design. It looks at noise, power and clock routing simultaneously. It
works both flat and hierarchically."
- an anon engineer
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