( DAC 03 Item 5 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Cadence Incisive & TestBuilder
WILD ENTHUSIASM: In a weird yet pleasant change of tactics, Cadence has
decided to offer everything including the kitchen sink under its new
"Incisive" program. Usually the EDA vendors like to nickle and dime you,
but this new Cadence strategy of everything-for-one-price has been met
with wild enthusiam by customers. (The customers see it as "free" because
they already own the Cadence tools anyway.) The C community appreciated
Cadence's TestBuilder open technology push from a few years back, too.
I guess Cadence expects to make money off the deal by volume package deals
and market share??? Regardless, the users are loving it.
Simulators
The big news in simulators is that more freebies are being thrown in
again this year, or at least included in the more expensive simulation
licenses.
Last year Cadence threw some really neat transaction based viewing
capability plus some C++ ties into NC-Sim and Synopsys threw VeraLite,
a subset of the Vera functional verification tool, into VCS. This year
Cadence will be throwing in what sounds like their own version of
Verisity, plus SystemC. Synopsys meanwhile is adding their CoverMeter
code coverage tool and will be adding property coverage to that tool.
Without trying these it's hard to tell if they're really great deals
that may put some people out of business, or if they're like those
all-in-one handyman tools where you might have done better putting the
money towards separate but more costly tools.
Cadence Incisive is NC-Sim plus a ton of other stuff. It supports
SystemC, which they are pushing this year. Note that Synopsys is pushing
System Verilog, and Cadence said they plan to support all languages,
including "extensions to Verilog". If you already own NC-Sim, you can
upgrade to Incisive for under $4K/year, and for that you get a TON of
stuff. You get a native compiled VHDL, Verilog and SystemC simulator,
dynamic PLS/Sugar assertion checking (static checking is due 3Q03 and
will be free), some sophisticated transaction level modeling, functional
coverage analysis, constrained random vector generation, linting, and
the Summit code coverage tool. They have easy ties to Quickturn
emulators, which they also own. They have one scheme that I'm not sure
I understand. If you buy a bunch of licenses, the Quickturn box you
get will actually have more gates than you paid for, but to use the
extra gates you must temporarily give up 9 licenses while you're using
them (I think that's it). I've tried the Summit code coverage tool and
it's a good tool, although I like the TransEDA GUI a lot better. Other
than that, I don't know how good these tools are but for this price you
almost have to give them a look if you own NC-Sim.
- John Weiland of Intrinsix
I only looked at Cadence Incisive because our main focus is on chip
simulation not on architecture testing. I like the direction Cadence
is taking toward Open standards. It really appears that Cadence is
getting it.
- Steven Jorgensen of Hewlett-Packard
Cadence Incisive only has dynamic assertion tools at the moment.
Dynamic assertions seem like a useful debug tool. However, is it really
worth the effort of putting all those assertions in, just to have your
simulator tell you there's a problem rather than looking at the waves?
I don't think so.
Where I can really see dynamic assertions being useful is for IP
developers who hand over designs and want to check they are being used
properly. They can then indicate to the integrator of the IP that he is
violating the IP interface spec. etc. Other than that, from what I've
heard NC seems to be keeping pace in terms of performance.
- Thomas Fairbairn of 3com
I attended the Cadence demo on SystemC, which they are now pushing hard
(note that two year ago it was Synopsys that was pushing it). They are
adding SystemC support to NC-Sim as part of their new Incisive simulator.
They recommend doing a SystemC prototype to create a golden reference
model/executable spec, and allow for faster simulation and earlier
software validation. They claim a minimum of 100X speedup over RTL and
showed an ARM design simulating at 50K cycles per second.
- John Weiland of Intrinsix
Synopsys and Cadence rule digital simulation segment. The new Synopsys
Discovery platform appears to be in response to the Incisive platform
from Cadence. The 2 big companies offerings are somewhat akin to stew,
throw everything (fresh or not) into the pot and serve it.
Are these "platforms" of real use or are they mechanism for account
control? They simplify the purchasing decision for companies, offer
benefits in reducing the number of suppliers a companies deals,
offer savings in purchase and support costs.
- [ An Anon Engineer ]
ModelTech? Great tool. Great tech support. Looking forward to a port
for AMD64 Linux architecture.
- Kevin Hubbard of Siemens
I had been following Cadence's work with TestBuilder. I liked that
TestBuilder was, or at least appears to be an open technology. I liked
its interface with Sim-Vision, and their tool Transaction Explorer, while
proprietary, left room for competition to do similar things because of
the open nature of TestBuilder. I thought the Incisive Compiler brought
to NC-Verilog the performance capabilities of VCS's Direct Kernal
Interface in bypassing PLI without forcing me to create code that would
work only with their simulator. The impression I have is that if I write
a test bench in TestBuilder, it will work with both VCS and NC-Verilog.
This is important because I have both simulators in house.
There also appears to be nothing stopping VCS from providing the same
performance improvements to my testbench in their compiler. This is in
start contrast to Synopsys' Initiatives to add C/VERA constructs to the
Verilog language, which forces me to only use their simulator.
My hope is that I will also be able have my Specman test platform take
advantage of the performance enhancements this should offer. Nothing in
the Cadence presentation led me to believe that this is not possible
because all Specman generates a heart is C code. Now perhaps there is
some catch that I did not see that would prevent Verisity from generating
code optimized for Incisive or Synopsys from being able to compile Test
Builder code using their Direct Kernal Interface, but I did not see it.
Sorry, I forgot to mention the weak points. There are two big holes.
The first area is Assertion technology. I cannot fault them totally
because the whole situation is a mess, but while they told me that if OVL
assertion won they would support them, they would not comment on a time
frame from approval. Also they did not appear to have an interface into
their debug platform for either an Equivalency Checker or a Model
Checker. Did you hear the rumor that they are buying Verplex?
The second area is that they are barking up the architectural/chip/block
verification unification tree. They seem to think that you can use the
same pieces to do architectural simulation, chip simulation and block
simulation, not realizing that the accuracy needed for block sims makes
the pieces useless for architectural sims and only slightly more useful
for chip sims. So what you end up doing is creating 3 different versions
of the same block with no easy way of verifying that they act the same
without simulations.
- [ An Anon Engineer ]
|
|
