( DAC 03 Item 32 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Nassda HSIM & Hanex & Critic
FINALLY ARRIVED: Let's see... You take your EDA start-up to IPO. Your key
tool, HSIM, gains dominant market share in its part of the EDA universe. You
spin off two more side tools (Hanex & Critic). Your customers like you, but
something's missing... Something's incomplete here... Until your biggest
rival, Synopsys, sues you! Congrats Nassda -- you've arrived! :)
Nassda HSIM is very slick. My main impression of HSIM is: "It just
works!" My TimeMill experience, a few years ago, was not good. This
was my primary reason for pursuing an alternative, such as HSIM.
- Tim Coots of Motorola
We have used Nassda's HSIM for silicon correlation analysis of a
technology test chip. The design had over 100 different memories. We
were able to run chip level simulation with over 10M devices and
complete RC back-annotation of both the signal and power nets. We were
able to accurately correlate the HSIM simulated memory timing and IR
drop to measured silicon.
- Andres Teene of LSI Logic
Xicor does analog and analog/mixed signal design including data
converters and analog front end subsystems. We typically use .18 and
.13 micron processes and have hundreds of thousands of transistors in a
chip. Historically, we did analog design using a SPICE transistor
level simulator. At smaller geometries, the issues got bigger and
bigger. Mask set costs are such a significant portion of the ROI
analysis that we need to insure first-time success on each design. One
of the key factors in guaranteeing that a design is correct the first
time is chip level simulation, which is impossible with traditional
SPICE simulators. So we looked at Nassda's HSIM and Cadence's
commercial tools for chip level verification.
When we first looked at HSIM, Nassda's demo took only 5 minutes to
work. We then tried a sample circuit, and HSIM got the same results in
1/2 hour that it took SPICE 14 hours to provide. We had also looked at
Cadence's Spectre-Verilog. It was a nice tool, with decent results
during the demo, but it was clumsier. It may have been more digitally
oriented and flexible, but Cadence's tool was not nearly as easy to use
as HSIM. HSIM looks just like a SPICE simulator, which makes it very
straightforward to use. It took us only 1 hour for the HSIM demo
meeting, we chose it, and we have had no trouble since. This is very
unusual, as typically it takes a solid month to evaluate and understand
other tools.
Some of HSIM's advantages:
1. Speed and Capacity. We used HSIM to verify the new analog chip we
introduced in September. We ran the entire chip through HSIM, and
it didn't even stress the tool. We were able to identify certain
performance parameters that we would never have seen with SPICE or
Verilog alone. We were pushing the limits of the design and
technology, so this made a big difference in the final product
performance. HSIM can run simulations in one day that would take
SPICE weeks. HSIM has been optimized to run transient analysis on
large, mixed signal designs and has successfully conquered the
standard convergence problems that has plagued SPICE simulators for
years.
2. Accuracy. HSIM just plugged into our flow and had no problems. We
are always amazed that given its speed, it is still quite accurate.
We have successfully achieved 10 bit resolution results by carefully
controlling the simulation parameters.
3. Full chip simulation. First, with HSIM you can see interactions
between blocks that you couldn't conceive of otherwise. A typical
example of this is power supply bounce induced by I/O's which can
feed back through the power network and create noise in the signal
path. A second way that we use HSIM's full chip analysis is to
check a complicated mixed signal control loop and make sure it is
functioning correctly. It is very common for a calibration loop to
have an analog section, an A/D conversion, and then Verilog coding
to analyze the data and make an adjustment in the analog signal
path. You end up doing an analysis of the signal in the digital
domain, even though you are in the analog domain. HSIM allows one
to simulate the entire function as a unit, over a long enough time,
to see that the implementation is correct and stable.
4. HSIM is actually very cost effective compared to SPICE alternatives.
Because of HSIM's high speed and capacity, we are able to have 4
designers share a license, versus getting one license for each of
them. It also takes a fraction of the set-up time and runs on
Windows, Linux or Unix. Considering the cost and performance of
today's PCs, it is hard to build a case for UNIX based design
environments. HSIM is not intended to replace SPICE simulators
such as Spectre, but to fill in the need for simulating the
functionality of very large circuits. One extremely cost effective
set-up that we have is to use PSPICE, which is much less expensive
than other SPICE simulators such as Spectre, and then have 4
designers share HSIM.
Nassda could make HSIM more user-friendly to change the trade-off
between speed and accuracy. There are lots of knobs to turn, and work
is needed to making the knobs more intuitive. We are sophisticated
users, so this is okay for us, but there is a learning curve needed.
If you just use the default for the options, you won't get both
accurate results and fast simulation time, a trial and error approach
is required.
We are currently evaluating HSIM's co-simulation feature. We must do
fast transistor level simulation early in the design process, with both
analog and digital blocks. Nassda has introduced a Co-Simulation
interface to run with NC Verilog. At first glance, this combination
looks very powerful and effective. The only big drawback is that NC
Verilog is not available in a Windows environment so we are forced to
pick either Linux or Unix.
Although we can't claim a competitive advantage by using a commercially
available product such as HSIM, anyone not using HSIM is at a clear
disadvantage.
- Roger Levinson of Xicor
Nassda's HSIM has been able to simulate our big mixed signal chips
almost out-of-the-box on every case so far. The largest case we had
HSIM faced is north of 33 million MOSFETs in size. Out-of-the-box to
me means no segmentation fault or core dumping, no more or less. It is
far less frustrating to debug error and/or warning reported by the tool
than have the tool giving up on you. This is no small feat as it
stands, considering the crude nature of the whole chip SPICE netlists
we have been feeding to HSIM. Found in our typical ASIC flow, they are
stitched together by some Verilog-to-SPICE perl scripts meant as input
to run LVS. This is an attribute of a well written tool that shows
high level of robustness.
- [ An Anon Engineer ]
HSIM is a good tool with its limitations. Ramp up time to learn the
tool compared to other analog simulators is longer because in order to
get correct results at a fast simulation time you need to turn many
knobs at least for RF simulators. It has very nice built-in debugging
capabilities. Once you get it to work (it may take a while for big
circuits) it is quite fast with reasonable accuracy.
- Arya Behzad of Broadcom
We have used Nassda's HSIM in our memory development characterization
flow for nearly a year. In general, I would rate the experience with
the tool on the positive side. We use it mainly for simulation of
fully extracted large memory instances to do a comparison of timing
against reduced net lists using a SPICE based tool.
In addition we use it for power (leakage and dynamic) characterization
since these simulations require the entire net list for accuracy.
As with any tool, it takes some time and experience to gain confidence
and learning which options to twist to give values that are reasonable
relative to tools (i.e. SPICE) used previously. This would be my major
complaint, but something not unexpected.
I will also add that the support from Nassda has been consistently
good.
- Craig Thrower of Virtual Silicon Technology
HSIM software continues to be a critical tool in our development flow.
It has the high simulation capacity for our memory compilers and NASSDA
has been responsive to keep the tool abreast of the latest silicon
technologies. Its ability to accurately simulate 90nm devices enabled
us to show first-silicon success in the past year.
- Raymond Leung of Virage Logic
In general, I find HSIM more useful for final verification of very
large chip cores containing a combination of analog and digital blocks.
Most analog blocks are stacked with digital calibration for currents
and caps, so the percentage of analog circuits in an "analog chip" such
as a radio is slowly dropping. You need to simulate pad to pad with
all transistors to establish functionality.
In addition to HSIM, we use behavior modeling for our digital blocks
and Spectre/HSPICE for our analog blocks, then join them with
SpectreVerilog.
One issue we have with SpectreVerilog is that the Verilog version used
to design and run the digital blocks is different from the Verilog
binary that SpectreVerilog uses. The current consumption of the blocks
cannot be measured, nor can the interactions with bypass caps, which
makes it hard to catch errors. Unfortunately, the alternative is to
let our digital designers design and simulate the digital sections and
the let our analog guys worry about the analog sections, and just hope
that the interface is what was intended! With the digital and analog
blocks so closely embedded with feedback these days, this sort of
approach is very unreliable.
Another way that we use HSIM is for circuits with high frequency
components as well as slow time constant components -- for example, a
phase-locked loop(PLL). Since I know that you like hard data, John: a
high frequency VCO in the gigahertz range needs a time step of 10 psec,
whereas a full sim of a loop lock can take upwards of 50 usec,
depending on the loop filter implemented. It would take 3-4 weeks to
simulate using Spectre to see minimal functionality of the PLL. It
might be faster to fabricate the circuit than to wait for sim results),
but that isn't feasible due to the expense. And if you include digital
calibration circuits, the task in Spectre is unfathomable on a
transistor level.
HSIM simulation run results are roughly 50 usec per 24 hrs for a
complex PLL block with 25K elements & 11K simulation nodes. So within
2 days, it is possible to simulate a full locking cycle as well as a
majority of the calibration all based on a transistor level schematic.
It is now possible to check over a few corners and check the
functionality of the calibration circuit with the actual PLL circuit
instead of a behavioral model.
One Nassda negative is that some critical commands are not well
documented and can be understood (or found) only via Nassda's technical
support. Although they are quite helpful, it'd be better to have a
well-documented tool. Unfortunately, a lot of Nassda "do's and don'ts"
are discovered only by trial and error, so it is quite difficult for a
novice to take advantage of their HSIM tool. Some people may be
reluctant to use HSIM because of this obstacle, but once the initial
simulation is successful, the advantages are well worth the effort.
What I like about HSIM are its fast DC convergence capabilities, which
is much faster than Spectre. (This is handy for measuring DC current
consumption of an entire chip and getting reasonable timing information
for power down and power on. These types of simulations are necessary
for catching any misconnected bypass caps that are added late in the
design process.) Another is that with a short script, it is easy to
convert the DC operating point from HSIM into an initial condition file
in Spectre and not have to wait for its DC convergence, which can take
up to hours for very complex circuits.
- Seema Anand of Broadcom from ESNUG 419 #5
Nassda has a tool that does clock tree analysis, from RTL or SPICE
netlist, and reports a critical path from your own STA tool but with
the clock skew from your tool. They also have a tool that creates
timing models (various formats including .lib) for full custom blocks
for use by your static timing analyzer.
- John Weiland of Intrinsix
Several of us attended Nassda's presentation at DAC on Hanex. Hanex is
a fairly interesting hybrid static-dynamic timing analysis tool that
works at the transistor level.
Hanex is more accurate than PrimeTime. For instance, transistor-level
operation enables accurate modeling of signal arrival times which are
critical for noise analysis and timing accuracy. Hanex currently lacks
ECO netlisting capability, so we can't use it for domino logic clock
phase assignment. Hanex is suitable for signoff timing and for custom
logic. However, the gain over PrimeTime is not worth the integration
cost to our heavily scripted RTL-to-signoff flow at 130 nanometer. At
65 nanometer, I think it is a different story.
Also, I should say I've never understood why Synopsys doesn't integrate
PrimeTime, Design Compiler, Physical Compiler, and Library Compiler.
In the past, Synopsys introduced new features in one tool, but you had
to wait six to twelve months to get the same features integrated into
the other tools and really use them. For instance, it is painful that
you only get certain attributes in PrimeTime and not in Design Compiler
and vice versa.
- Scott Anderson of ST Microelectronics
Here are my brief comments on Hanex -- please keep in mind that I have
not used the tool and have only seen a presentation.
Hanex seems to me to be the next evolutionary step toward providing a
more robust STA analysis for your design. Coupling static/dynamic
simulations in one tool is unique and if done right can be a
significant advantage as it should provide a higher degree of accuracy.
- [ An Anon Engineer ]
The Nassda Hanex demonstration was conducted strictly under NDA, so I
can't say anything much about the product's features. I will say that
the NDA was clearly just a marketing ruse to generate interest. The
'fundamental technology breakthrough' which Nassda call 'hybrid TA'
turned out to look virtually identical to the approach adopted a well-
known EDA company in the early 90's. Maybe it's different, but there
was no way of forming that conclusion from the presentation. The
presentation was frankly vacuous, talked about some very obvious things
to get right in TA. Absolutely no enlightenment. I was sorry that my
team had wasted time on Nassda when there is always too much to see at
DAC.
- Simon Knowles of Icera
Here are my observations from the Nassda Hanex demo that I saw at DAC.
Nassda describes Hanex as a "hybrid" timing analyzer aimed at full-
custom designs. Hanex traces paths like a static timing analyzer but
instead of using table-lookup models for delay calculation, it
simulates the paths using a circuit simulation engine under the hood.
The clock tree is also traced and simulated separately to give clock
arrival times at every latch or flip-flop for performing setup and hold
checks.
Hanex has mechanisms for including cross-talk effects into timing
simulations. The user is required to specify transitions on a selected
list of aggressor nets. These are propagated through static logic and
are used in simulations. Dynamic gates and some flavors of latches and
flops are recognized automatically. Pattern-matching is available for
identifying more complex structures. Given the many different full-
custom design styles, getting the recognition algorithms to work on a
particular design is bound to be a non-trivial task.
Other than the aging PathMill from Synopsys, there are very few tools
in the full-custom transistor-level timing analysis space. Hanex has
the potential to complement PathMill and fill some gaps in this niche.
- Mahesh Sharma of Advanced Micro Devices
I saw a demo of Nassda's Hanex at DAC. I haven't used it yet, so this
feedback is only based on the demo that I saw. We do use Nassda's HSIM
however.
Hanex uses a hybrid approach that combines both static (cell level) and
dynamic (transistor level) timing to analyze critical paths.
Dynamically, Hanex does clock tree analysis (given the clock source)
for improved accuracy on clock skew, simulates crosstalk effects from
backannotated RC parasitics, and considers voltage dependent
capacitance, Miller capacitance,and nonlinear input slopes for greater
accuracy. It reads .lib for stdcells. But at this writing, Hanex does
not yet support sdc constraint format used by PrimeTime. It's claim to
fame is reducing pessimism from typical cell based STA tools and
improving quality of the designs by incorporating dynamic analysis at
the transistor level.
Today my company uses PrimeTime, but I think PrimeTime is starting to
run out of steam because of DSM, eg. noise issues and crosstalk. DSM
effects pull us toward dynamic analysis, yet capacity issues pull us
toward static analysis. We look at hybrid tools to solve this. Hanex
is equipped to look at dynamic effects of those features, in that sense
it is suitable, i.e. from a DAC demo technical standpoint. But from a
business standpoint, we can't just throw away PrimeTime.
We do trust that transistor analysis is more accurate and correlates
better, but don't do it for overall timing analysis because of
capacity. The theory is that Hanex will have the right accuracy with
the capacity, but we would need to evaluate it to verify this. If it
diverts from the flow, like Hanex does, it is okay if you really need
to do it.
A Hanex DAC demo vs. PrimeTime comparison:
- PrimeTime relies on characterization of the library, and the
characterization is done in a certain manner, e.g. for a 200 Mhz
speed/frequency. In general, this exact speed is not what the
library is characterized for. Designs may run slower or faster, and
the PrimeTime library is not characterized for that. So you may not
see the same quality with the actual chip.
- PrimeTime is padded (guardbanding) for worst corner and best corner,
where everything all will fall in between. It can't predict nominal
corners.
- Hanex's strong point is that it allows you to not rely on the
library, but instead do actual analysis based on transistor and
SPICE model. Hanex gives a middle point to deal with capacity and
acccuracy. So you are actually doing timing analysis based on true
model vs. library. So you have a better handle on your prediction.
- For Hanex to replace PrimeTime, it needs other capabilities. e.g. it
needs to be able to deal with IR drop.
- When I was at DAC, I asked if Hanex could accept PrimeTime constraint
input, but they said it didn't yet. So Hanex doesn't plug and play
right now, which is important.
Hanex may be easily mistaken for PathMill. But it is a hybrid, so the
two tools are different. Besides, Hanex has other capabilities like SI
analysis that PathMill lacks. Hanex cannot replace PrimeTime, as least
not any time soon. But Hanex may be used to improve the design quality
on top of PrimeTime.
- Ken Wong of Conexant from ESNUG 417 #11
I am impressed with Nassda's Critic. It simply reads an SPEF and/or
PrimeTime report (critical paths list), and runs transistor level
simulations for the clock paths and whatever critical paths
specified,it also takes into consideration the crosstalk effect on the
delay. This makes it so easy to verify the max clock speed of the chip
and the critical interface timing (such as DDR). The only thing that
I think needs to be added to the tool is the crosstalk glitch
simulations on the noise/glitch sensitive points -- with that the tool
will be a great complement to the STA & static noise analysis tool.
- Richard Liang of Solarflare Communications,Inc.
From the DAC demo that I saw, Critic is a tool for simulating critical
paths identified by static timing analyzers such as PrimeTime. Given
gate-level verilog, parasitics in DSPF/SPEF format and SPICE netlists
for standard cells, the tool can trace paths from STA, sensitize them
and simulate using HSIM. Critic is meant only for cell-based designs.
As far as I can tell the only utility of this tool is for verifying the
Cell timing libraries, so I don't see where it adds value.
- Mahesh Sharma of Advanced Micro Devices
Earlier this year I evaluated Nassda's Critic. Critic is transistor
level static timing analysis tool. It uses their HSIM engine for
a transistor level simulation of the clock network and then simulates
each of the critical paths specified in the STA report. We found
that Critic is easy to setup and integrates easily into cell based
design flow, it uses PrimeTime reports and chip back-annotation files
that are in our design flow. It's not a replacement for PrimeTime, but
can provide a higher level of accuracy especially when the DSM becomes
more significant.
- Andres Teene of LSI Logic
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