( DAC 99 Item 7 ) ----------------------------------------------- [6/25/99]
Going beyond C translating and into the C HW/SW co-design are the standbys
Synopsys (Eaglei), Mentor (SEAMLESS), CAE-Plus (ArchGen), CoWare (N2C)
( http://www.coware.com ), NuThena (Foresight) ( http://www.nuthena.com ),
VaST (CoMET) ( http://www.vastsystems.com ) and Summit (V-CPU). The new
kid, TransModeling ( chip@transmodeling.com ) offers simulation over
distributed CPUs. All of these approaches offer a 'Promised Land' of
"happily blurred lines between what part of your design is ASIC and what
part is microprocessor(s) running software", but the reality is you always
have a well defined ASIC part and a uP-running-assembly part if you use
these tools. You might as well add using those olde Synopsys LMC C BFMs
with a Verilog PLI to this supposedly 'new' Mix-N-Match world of C/Verilog
HW/SW co-design 'tools'. ( http://www.synopsys.com/products/lm ) Yup,
the more things change, the more they stay the same!
"Are you trying to decide between using a processor core in an ASIC
vs. pure HW? Or, just whether to use an off-the-shelf processor
versus gates? Some random thoughts..
- Obviously, you need to size your processor. How many MIPs do
you need, 32-bits?, 8-bits? etc. etc. Use a conservative
technique like RMA to analyse your SW tasks and analyse your
system in terms of throughputs, latencies, etc. Analyse your
memory requirements. You can do a lot of this with just a
simulator/debugger.
- Sometimes, a small cheap CPLD or FPGA can augment your processor
and provide input/output processing, FIFOs or some DSP that
enables you to use a much smaller processor than if you tried to
do absolutely everything in the processor.
- You can get good, cheap GNU or other compiler/simulator/debuggers
that will help you very quickly get some performance and memory
metrics before committing to a particular processor. Vendors
will often loan you tools for such evaluations.
- In my experience, processor-based solutions demand more detailed
system analysis than HW approaches since running out of MIPS
can be death, whereas adding another HW FIR filter to an ASIC
is more of a "graceful degradation" of the solution.
- Electrical properties... Be real careful about PLLs when
considering power consumption (they're an analog component that
don't folow CMOS power rules). Check out the "sleep" modes
that processor cores offer. If you really care about power and
sleep modes aren't an option, then power-crafted HW might have
an edge.
- Don't always assume that you have to have 32-bit this or that or
multiply, etc. Compilers and their real-time libraries can
emulate such things (at a price). Benchmark with a compiler and
simulator and maybe you don't really need a DSP or 32-bit uP.
- Processors (at least the ones with good tools support) are IP
that you have to pay for.
How will you boot your processor? Flash? That costs, whereas custom
ASIC doesn't. Memory costs can swamp other costs. And finally, don't
forget auxillary costs associated with processors like supervisory
circuits, memory, etc."
- Tom Coonan of Scientific Atlanta
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