( DAC 99 Item 22 ) ----------------------------------------------- [6/25/99]
MAD DOGS AND ENGLISHMEN One of the more unexpected new tools from this
year's DAC was ChannelSim from Cogency. ( http://www.cogency.com )
Essentially they greatly reduce power consumption and noise generation by
promoting the design of asynchronous (they call it 'self-timed') logic.
They also claim speed-up of large combinational logic blocks like 32-bit
multipliers, etc. It's kind of odd stuff, this asynch based design. The
Cogency web site has an async tutorial, but you may also want to check out
Theseus, a company making asynch-based chips ( http://www.theseus.com )
and the University of Manchester's Asynchronous Logic Home Page at
( http://www.cs.man.ac.uk/amulet/async ).
"Most interesting niche tool? I think it is the Cogency tool for
self-timed (asynchronous) synthesis. The tool attracted me from
the practical point of view. It integrates neatly within our
existing flow like DC Synopsys, DAI's SignalScan and VCS."
- an anon engineer
"Asynch designs will be the only way these future monster Systems
on a Chip will work ten years from now. No, wait, I'll be bold
and make that five years from now. This is the most fun I've
had since the introduction of logic synthesis 12 years ago."
- Michiel Ligthart, who was employee #5 at Exemplar and is
now employee #15 at Theseus Logic
"Session 7: Asynchronous Logic Synthesis
Steve Nowick of Columbia U. presented an overview of asynchronous
circuits. He kept saying words like 'difficult' and 'complicated'
and 'hazards'. Their experimental burst mode FSM design tools can
synthesize about 15 gates. (Yes, it's that small. 15.) Ken Yun of
UC San Diego talked about timed asynchronous circuits. These are
circuits whose timing properties are very carefully analyzed. They
can run very fast, but there are no tools for them. Overall, the two
made asynchronous circuits seem difficult. Alex Kondratyev, U. of
Newcastle, mentioned that more concurrency does not mean a faster
circuit, and showed some examples. Shai Rotem and Ken Stevens, both
Intel, discussed timed asynchronous circuits, and the EDA tools
needed. They needed tools, since it's exploring a new territory."
- an anon engineer
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