( DAC 99 Item 34 ) ----------------------------------------------- [6/25/99]
"The buzz words seem to be "one-pass" and "timing closure". I heard
horror stories of 4-17 iterations required for designs in order to
meet timing closure. To deal with this problem Synopsys, is releasing
Chip Architect and Avant! is releasing Jupiter. Both are front end
floorplanning, quick synthesis, placement, and global routing tools
that pass interconnect information to Synopsys Design Compiler."
- an anon engineer
"If Avant!'s product is based on ACEO, then we have a good idea of
what it is and consider it a non-threat."
- Sanjiv Kaul, Synopsys VP. ACEO is Avant!'s synthesis tool.
"I talked to TI to get a better understanding of how their new tool
flow is expected to work. With their push to using Avanti layout
tools (Planet-PL), TI pledges that they will initially couple their
support engineers with design teams to jointly layout designs
together. Within about a year, they plan to push the floorplanning
solely into the designers hands with minor assistance from the field
engineers. They plan to evaluate using the new Jupiter tool from
Avanti, but they have no commitment about it in their design flow."
- an anon engineer
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