( DAC 99 Item 36 ) ----------------------------------------------- [6/25/99]
"Magma: FLOOR DEMO
Integrated technology mapping, placement, routing, and timing. They
take a synthesized netlist, unmap it, use technology-independent
variable-strength gates, assign strengths to meet timing (taking
loading into account) and finally place & route. Midway through
the flow, before P&R, they provide a "MPG" -- a performance
guarantee that they will be able to meet timing.
Magma: SUITE DEMO 1: "BLAST FUSION"
Two part flow; MPG given between the two. Timing constrains in
Synopsys Primetime format. Crosstalk taken into account during track
routing (router is global; then sub routing, then track routing, then
final). Overall flow: verilog, lef, .lib in, GDSII out. Extractor:
field solver to produce rules, then used by Quasi-3D extractor,
including cross, lateral, area, and fringe caps. Have tested on 1M
placeable objects, ran in <2GB memory (this was a bogus netlist).
Magma: SUITE DEMO 2: "SIGNAL INTEGRITY"
This works during the "blast builder" phase, which is also doing
timing analysis. Noise target: fraction (e.g., 25% of Vdd). Current
analysis: crosstalk, noise/delay optimization, IR drop analysis.
Planned: EM (AC & DC). Basics: added crosstalk awareness to router.
When tool does not work, can do shielding through the TCL interface.
Wire sizing: limited capability. Concept of Magma's stuff is "logical
effort" which is published. Incremental net-by-net extractor. Can
write spef/dspf. Timer: .lib, incrementally better interconnect.
Supports PrimeTime constraints. Also look at drive/wiresize, for
signal EM. Includes buffer insertion; can use TCL to do shielding.
Buffer insertion manages both long wire delay, and breaks up coupling
caps. Track router observes timing windows. Global routing drives
buffering for noise. Router is interactive; can rip up and reroute
if solution is not correct for noise at end. Example (live demo
claimed): 20k gates, 5k placeable cells.
Monterey: FLOOR DEMO
Simultaneous synthesis, P&R, extraction, timing, noise analysis.
(Note: noise analysis is not really there.) PD dissolves/flows
cells across floor planned boundaries, unlike Magma. Claimed
integration with standard flows.
Monterey: SUITE DEMO: "Dolphin"
Simultaneous P&R, timing, logic optimization. Open architecture for
cost function. Model refined during design flow and across views.
Cells migrate across floor planned boundaries for both timing and
congestion. Timer is PrimeTime compatible. Reads simple Synopsys
constraints. For complex ones, go into Design Compiler then do a
"write_script" to get constraint file that tool can read. Tool
does timing, buffering. Simultaneously creates clock tree while
placing latches. User specifies preroutes as desired (e.g., I/O's,
megacells, routing of global clock). Partnered with Coyote Systems'
BEM tool (field solver?). Still working to define ECO flow with
beta partners. Shape based router; tool can do width selection. Scan
chain reordering to reduce congestion. Recommend: ATPG after P&R.
Largest example: 280k cells, 800k gates, 1200 microns on a side1.
1-2 days run time on a multiprocessor (Sun 6500, 24 processor,
24 GByte). Input: .lib, netlist, lef, Synopsys timing constraints.
In-memory data model, checkpoint capability.
Tools historically have a 5 year lifetime, they'd like to do better.
Said HP N-class machines have much better memory bandwidth than Sun."
- an anon engineer
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