( SNUG 00 Item 8 ) --------------------------------------------- [ 4/05/00 ]
FUTURE SHOCK: One odd discoveries I made at HDLcon'99 was a lone vendor
booth in the hallway by Innologic Systems. I didn't quite fully understand
what they were saying about doing "symbolic simulations", but in my gut I
felt the same way I felt when I visited my first formal verification
equivalency checking booth years ago. (And now equivalency checking is a
mainstream part of many large chip design flows!) Check this "symbolic
simulation" stuff out at: http://www.innologic-systems.com and tell me
what you think.
"Worst Booth: Frequency Technology. I think they must have a very
interesting product, but couldn't learn anything from the booth."
- an anon engineer
"Biggest lie? Don't know, because Cadence wasn't there. (Yes, it's a
cheap shot but they deserve it.)"
- an anon engineer
"At the vendor fair I saw a tool from Ultima called ClockWise. Caught
my attention as a stand alone clock tree generation tool since Chip
Architect/PhysOpt does not have this capability yet (but will soon).
However, this tool claims to be able to use clock skew as an advantage,
moving the clock edges to fix setup/hold times. Their idea both
intrigues and scares the hell out of me. This would have very serious
implications on hold violations on scan flops."
- an anon engineer
"Hmmm... You bought LEDA for RTL DRCs. OK, I'm listening. Talk to me."
- overheard at the SNUG'00 R&D night
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