( SNUG 00 Item 11 ) -------------------------------------------- [ 4/05/00 ]
"People are missing the point here. We need levels of abstraction to be
removed -- not added! In the not too distant future we'll need
RTL-level sign-off and we'll also need good RTL-level power, area, and
timing estimation tools."
- Steve Golson of Trilobyte Design
"We already do RTL sign-off today. It doesn't make sense that every
designer knows synthesis details. We just have one engineer in our
group that does that and the rest of us write the Verilog RTL."
- Paul Zimmer of Cisco Systems
"The status right now is we're at 55 bits."
- Aart de Geus, CEO of Synopsys, joking about 64 bit Design
Compiler coming out by the end of the year.
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