( SNUG 00 Item 14 ) -------------------------------------------- [ 4/05/00 ]
THE SUPERLOG DEBUT: Besides all the talk of switching over to C and C++
at both SNUG'00 and a lot more at the proceeding week's HDLcon'00, yet
another language finally had it's "coming out" party: Superlog. And
once I find a stable new home for DeepChip.com, I'll have the slides
for Superlog up there. Last year I ridiculed Simon Davidmann, the CEO of
Co-Design, who makes Superlog. But this year, after seeing the Verilog
users I respect express a real interest in Superlog, I've got to eat a
little humble pie now. The big Superlog selling point that attracted
these design veterans was that Superlog was being designed as a super-set
of Verilog. That is, present day Verilog will run within Superlog with
full compatibility -- yet Superlog would have extra features that Verilog
lacks today. And with Phil Moreby, the father of Verilog, on board with
the Superlog team, this is no empty promise. http://www.co-design.com
"I don't see Superlog as a new language, I see it as an evolution of
Verilog. You can use whatever language you like as long as it is
compatible with Verilog. We are using Verilog exclusively for design
and verification and by now we have 50 million lines of Verilog
code that we are not going to replace. I know some C but I am not
using it for design or verification, neither is anyone else that I
know around here. C++ is even more of an unknown! Yes you can make
C look like Verilog if you are using some of the tools like CynApps
but the designer have to rewrite his code several time to make behave
like Verilog and then what is the point. Surely there are instances
where C is a better language, but using C in isolation and trying to
link it to a Verilog simulation via the PLI I don't think is the right
solution. A much tighter coupling between the two languages is
required and ONE way of achieving that is SuperLog."
- Anders Nordstrom of Nortel Networks from ESNUG 345 #10
"Please don't allow every special interest group to add their special
construct to your systems language. I saw this before on the VHDL
committees and it's an unworkable mess."
- Bill Billowitch of Intrinsix
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