( SNUG 01 Item 2 ) --------------------------------------------- [ 3/28/01 ]
Subject: The Bigwig's Big SNUG Speech -- Was Aart Distracted?
NOT ALL THERE: After 10 years of giving very interesting keynote addresses
keeping the audience (and even his Marketing staff) on the edge of their
seats with interesting technology leaks and snappy Q&A, this year Aart de
Geus, the CEO of Synopsys, gave a speech his Marketing staff could have
given. It was sad to see. Usually Aart's on the top of his game. OK, so
some of the engineers expected Aart to know all sorts of Synopsys technical
minutiae, but the guy's a CEO -- he can't do that for all 78 EDA products
he manages. Don't get me wrong; it's *GOOD* to ask Aart these questions
because *someone* will answer them! But I was floored when I asked him
about bad customer reactions to Chip Architect (ESNUG 364 #1) and Aart
replied about it being a *pricing* issue! (This is with customers howling
about Chip Architect not working as a *hierarchical* tool! He should have
known about that one. It's only 1/3 of his physical synthesis offering,
after all...)
"Did you notice Aart "promising" discounts on Chip Architect to
everyone? :-)"
- Paul Gerlach of Tektronix
"...yawn. Sorry, Aart... not much new, but more hope to see more soon.
I wanted more on topics like Linux, 64 bit support, cross talk in
timing delays, & the new tool for sharing views on machines between
Synopsys & customers out in the field for debugging problems
(ViewConnect.) I didn't get to see any of this at SNUG, but heard
about a good demo on it done at EuroSNUG."
- Chris Kiegle of IBM
"In addition to the usual state of the industry stuff, Aart usually
gives some insight into what's coming soon. At the Boston SNUG
(5 months ago), he mentioned the following goodies:
- Synopsys Professional Services is presently doing RTL to GDSII.
- PrimeTime is now in beta with crosstalk analysis capability.
- Signal integrity coming into Physical Compiler
- Synopsys is working directly with tester companies to bolster
their test offerings
In this SNUG speech, it was far more interesting what was NOT said!
Unless I sneezed and missed something, Aart said NOTHING in his
keynote address. What about clock tree synthesis? What about
Route 66? What about signal integrity? What about testability
improvements? Aart, where was the beef?"
- Bob Wiegand of NxtWave Communications
"The Q&A was weak but Synopsys has performed well this last year
so the users really didn't have much ammo. I did like the fact
that ASIC starts are basically constant which I found surprising.
I noticed that SystemC was talked about again but now with the
realization that it will not be replacing Verilog/VHDL anytime
soon. This was in contrast to Aart's speech last year when a
large majority of the talk was on SystemC and the fact that it
would take over the world.
It was nice to see that Linux is getting the ports it deserves.
We will have an issue with Linux hardware not being as large as
SUN/HP but it is catching up."
- Tom Tessier, t2design
"Unfortunately this year Aart didn't make many predictions/promises as
he was warned by his marketing managers. Here were some quotes:
- There is more value in a new car's semiconductors than in
its steel.
- The current problems with the economy put design in the
forefront.
- Physical Compiler will have power synthesis, datapath,
clock tree synthesis and DFT tools.
- Design methodology has a profound impact on the success
of the players as there are more handoffs.
- 6 Design challenges: Timing closure (causes largest schedule
slips), verification, IP and systems integration, test,
signal integrity, power
As usual Aart's speech was very well attended."
- Joe Gilray of Agilent
"Actually I didn't think it was too bad. Aart skimmed over some stuff,
and I still think there is holes in the Synopsys flow that need
addressing (their own router engine will help)."
- Chris Byham of Philips Semiconductors
"Synopsys has changed the licensing daemons for it tools. The new keys
won't run the old revisions of the tools. I tried raising this issue
at SNUG, but Aart just said "why would you want to run old revisions of
tools?" Here's why. We taped out chips at particular revisions of
tools: tools for simulation, synthesis, layout. To reproduce the
chip, we need to be able to rerun those *exact* tools, including which
revision of the tools. Running older chips on new tool revisions
might require extensive work. When someone suggests that my chip in the
field has a bug, I need to come back with a response, quickly."
- an anon engineer
"Key note - CEO Synopsys - March 13 -15 of 2002 will be the next SNUG.
Since 1999 SNUG has grown 31.1%, predicting another 10-22% for year
2000. VHDL Synopsys simulation is 5x slower than Verilog. Scissero
is a new VHDL sim tool that will be 5x faster than VSS. Notes that
the cost of testing a design will equal the cost of creating a design.
At .15u cross talk delay will start to equal interconnect delay. A
good quote from Aart was "Push on us to be as open as possible with our
interfaces" (I wish it were so!). 64 bit version of PrimeTime out now.
DC 64 bit will be out soon. DC on LINUX (red hat) was released two
weeks ago. (485 people attended SNUG this year)."
- [ Kenny, from South Park ]
"Something very fishy is going on at Synopsys w.r.t. the Clock Tree
Synthesis in Physical Compiler. I asked the question about it last
year and Aart said "Its the top priority and it will be release by
December". This year I asked him same question and got the same
answer. At the R&D night, none of the Synopsys engineers could give
me a clear answer. Is Aart hiding something??
Apart from his first 15 minutes that were interesting, the rest was a
marketing pitch."
- Himanshu Bhatnagar of Conexant
"Clock Tree Synthesis in on the top of our queue. I don't want to be
assasinated by the Marketing manager for it, so I can't give out a
specific date as to when it comes out."
- reply by Aart de Geus, CEO of Synopsys
"6) Signal Integrity -- Here, Aart could only hint at a solution
'soon to come'. This is probably tied in with the detail
router solution to be integrated into Physical Compiler.
Everybody at Synopsys is being notably cautious about
revealing any sort of release date for this stuff. I suspect
it's because they require a major update to their internal
timing engine in order to handle detail routing properly
(ie, integrate the PrimeTime engine into Physical Compiler.)"
- Rich Conlin of Paradigm Works
"We are running into the same PDEF 3.0 for PhysOpt problem Bob reported
back in March 2000 (11 months ago!) Wouldn't you think Avanti would
have fixed this by now?! Could anyone who has them please send us the
Scheme scripts used to process the Avanti PDEF 2.0 files for PhysOpt?"
- Andy Pagones of Motorola ( from ESNUG 365 #1 )
"I read some postings on ESNUG referring to the difficulty of using
Apollo as the backend to Synopsys Physical Compiler. We are
particularly having trouble reading PDEF 3.0 into Apollo and we have
tried the various methods that have been suggested (pdef2adb and
Scheme scripts). Do you have any additional information on this?"
- Scott Marvenko, Department of Defense [ Someone during
Aart's Q&A asked exactly this same question. ]
"Here's how you can help. Push on us and the other guys to make it
happen. If we push on Avanti or Cadence, nothing happens. If you
push on them, something happens."
- reply by Aart de Geus, CEO of Synopsys
BTW, Scott's PhysOpt/Avanti PDEF 3.0/2.0 was solved last week in ESNUG 367.
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