( SNUG 01 Item 9 ) --------------------------------------------- [ 3/28/01 ]
Subject: Tera Systems "TeraForm"
THE SMELL OF BLOOD: Like wolves circling a wounded deer, it doesn't take
much imagination to see Tera Systems TeraForm tool going after the Synopsys
niche left open by a wounded Chip Architect. TeraForm is a hierarchical
design tool that does floorplanning and it drives DC and Silicon Ensemble.
(Sounds an awful *lot* like Chip Architect, no?)
"I would be very interested in knowing whether anyone has tried
Tera Systems "TeraForm" tool. Basically it's a fast RTL-to-physical
design-planning/analysis tool. It's supposed to give you a quick
idea of where your critical paths will be.
One bottleneck I see there would be getting your Synopsys tech. library
converted to their "TeraGate" library.
I'm also not convinced that they can accurately predict the results
of other vendors' synthesis and layout tools. Maybe you can get a
gross "levels-of-logic-between-flops" type of feedback, but I don't
see how their "unique structural abstraction that accurately models
logic, layout, and timing" (quote from their brochure) could be so
accurate. Has anyone found it really useful, and how well did it
correlate with their final synthesis & P&R results?"
- Kris Monsen of Mobilygen Corp.
"TeraForm finds a chip solution at the RTL level and then drives DC
and SE for the detailed implementation of the design. I've done two
designs with TeraForm: 1) a 350 Kgate core with 9 RAMs, and 2)
1.2 Mgates with 64 RAMs. Both designs had many clock and tricky
timing exceptions involved. After floorplanning in TeraForm, I walked
through DC (budgeting, dcsh scripts, set_load & custom WLMs) also
inside TeraForm. It passed the design floorplan on to SE in DEF.
TeraForm lets RTL designers to do early design exploration (timing,
floorplanning issues and power planning) by automatically synthesizing
RTL to their higher level TeraGate components. (These 'TeraGates' are
characterized for our fab's and are not just generic macros.) You
then do 'TeraGate' P&R at that higher level. Timing estimation and
budgeting is integrated with automatic floorplanning (this is what
they call virtual prototyping.) The TeraGates are macros like adders
and multipliers, which gives the system an order of magnitude greater
capacity and faster turnaround times than gate-level tools. It lets
do full chip design exploration very early in the design process at
RTL (before synthesis) to identify the chip level issues.
I've found that this way of designing with TeraForm to be about 10X
faster than doing the same things at gate level."
- Arun Balakrishnan of NEC Electronics
"I have been working with the TeraForm tool from Tera Systems for more
than a year now. Recently I was called on to investigate 2 designs
that were causing some major headaches for our design center engineers
here at LSI. These were large networking chips that were having
problems going through the back end and meeting timing.
With the TeraForm tool I was able in a matter of hours to identify the
same critical timing paths in the RTL that had taken weeks to find with
the traditional methods. I was able to find opportunities for retiming
and resource sharing within the designs and also identify logic that
could be restructured for area and timing improvements.
The tool has a nice GUI, the RTL cross probing and ability to view the
generated schematics and timing all in the same environment make it
easy to explore the design and see where the problem areas are. The
logic structures is presented at a level higher than gate, which makes
it _far_ more useful than gate level schematics. TeraForm provides
sufficient information for you to re-architect and/or re-budget your
design. (In my position, I have to interpret customer designs for
back end implementation.) I see TeraForm as a real productivity gain.
- Gopi Kudva of LSI Logic
"I am a repeated customer of TeraForm. I bought the tool again when I
changed jobs recently. I use it for RTL analysis and design planning
of ASICs. I have used TeraForm on chips ranging from a few hundred
K gates to multi-million gates with clock speed ranging from below
100 MHz to above 200 MHz. I used TeraForm mostly in synthesizing other
people's designs. They give me RTL, I responsible for GDSII.
I've found it useful in identifying inefficient structures in RTL
descriptions. By inefficient structures, I mean logic that eventually
causes routing congestion problems and bad timing later at the
synthesis and place & route stages. Complex MUX or datapath structures
are classic examples; also "memories" - array of array of flip-flops
(basically all large regular structures).
These problems are almost impossible to see by just reading their
original RTL files (those big constructs can often be described in
very few lines of code). By the time I see these problems after going
through the entire backend, it is too late and too painful to change
the RTL. TeraForm let find and fix many routeability and timing
problems in the RTL, before spending any time on synthesis and
place & route -- or at least I am made aware of those problems to
find ways how to deal with them without changing the code.
The tool creates a floorplan directly from RTL and derives routing
and timing information from that. Of course that's not as accurate
as a placed and routed design, but it is close enough to identify most
of those problems.
To create the floorplan, it abstacts the RTL into "TeraGates" which
are basically RTL primitives (Mux, Add, Mult, Register etc.) and makes
a size estimate (e.g. 32 bit wide, slow implementation, strong driver
for fanout/length). It then creates a floorplan by actually P&Ring
those TeraGate elements (iterating implementations and drive-strength
in the process). Simply looking at that floorplan and identifying the
"big" elements and routing hot spots then points out those problems
(e.g.reg[32:0] my_reg[48:0]).
This is the only tool I know of that integrates datapath partitioning
and floorplanning. It's especially useful to find out whether a design
is suited for datapath and whether using datapath actually provides
any benefit. (Often, but certainly not always the case!) In case
datapath does get used, the RTL does not have to be rewritten, as the
resulting design already contains all the instantiations of datapath
elements - next to the rest of the logic which gets synthesized
as usual."
- an anon engineer
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