( SNUG 01 Item 11 ) -------------------------------------------- [ 3/28/01 ]
Subject: Synopsys NDA "Hidden Dragon" & "SmartClusters"
LIAR! LIAR! PANTS ON FIRE! Aart may be considered trustworthy by the EDA
masses (at least when he's being compared to Rajeev Madhavan of Magma or
Ray Bingham of Cadence), but through a buddy or two or six at Synopsys, I
heard that on the day after his SNUG'01 Keynote Address, Aart went to an
"All Hands" meeting with the Synopsys Physical Synthesis team to discuss
any & all issues with PhysOpt, FlexRoute, and *especially* Chip Architect!
Aart was *presenting* at this employee-only meeting and the Synopsys AE's
who support Chip Architect grilled Aart about what to do about Chip Arch's
extraordinary problems. Aart knew all along about the hideous problems
Chip was having!
And now this story gets more interesting.
Yesterday, Synopsys Corporate sent out a memo to the Physical Support Staff
outlining Chip Arch's troubles and a new product from Synopsys R&D that's
supposed to fix Chip Arch's flaws. And I managed to get a copy of this
memo! (It's up on the "Downloads" section of http://www.DeepChip.com until
the Synopsys lawyers make me take it down! Get it quickly, folks!)
Here's my favorite quote. (KEY: PSS is Physical Synthesis Staff, BU is
Business Unit, CA is Chip Arch, PC is Physical Compiler)
"I would like to thank the PSS field organization for the excellent
feedback received at the last all-hands meeting in Mountain View.
Let me re-iterate that the BU hears you loud and clear. This response
should provide insight into product planning and priorities within
the BU.
We need to address a number of CA issues:
1. Missing or overlapping functionality between CA and PC
2. CA IPO capabilities that never delivered on
the promise of timing closure
3. CTS missing from the flow
4. Complex. Some commands are confusing in CA
5. Performance. Some commands are slow and require too much memory
However, let us not forget that Chip Architect has also had significant
success in the marketplace. Large customers such as Toshiba,
Matsushita, ST and Motorola have all had success with CA. Over 25
customer tape-outs demonstrate that CA can be used in a real-world
production flow. We should recognize that the combination of CA & PC
is providing customers with a compelling solution.
Existing and recently announced solutions from Cadence and Avant! for
hierarchical design continue to be very weak and vulnerable. Start-ups
that are trying to address the issue are providing incomplete and
risky solutions."
- from "PSS_CA_Mar2001_all_hands_response_final.doc"
They're clearly discussing CA's weaknesses and trying to buck up the morale
of the field staff stuck supporting CA. The fix is "Hidden Dragon":
"Project Hidden Dragon
Hidden Dragon (derived from Hierarchical Design) is intended to solve
the most critical hierarchical design problems faced by our most
demanding customers. What follows is a brief 10,000 ft. view of
project Hidden Dragon.
- Delivers a scalable 25M-100M gate chip integration flow.
This flow leverages successful technology from Physical Compiler
for critical phases of the flow in which the netlist is modified.
Physical Compiler "engines" will be used to perform CTS and IPO
at both the block and chip level.
PrimeTime and Physical Compiler engines will be used to build
timing (ILM), DRC, constraint and physical abstracts of a block.
These abstracts can then be used to integrate the complete chip.
This involves optimizing chip level timing, CTS and scan chains.
PrimeTime will use the same abstracts to perform chip-level timing.
- New approach to hierarchical floorplanning that uses the full chip
context to produce high quality floorplans from routability and
timing perspective.
This solution will utilize newly developed SmartCluster technology.
Smart clustering traverses the hierarchy of a chip and retains the
minimum data necessary to create a good floorplan, macro placement
and pin assignment. This approach requires a much smaller
fraction of memory and compute cycles. Initial results show that
SmartClusters offer scalable 10X-1000X improvements in capacity and
runtime as compared to detailed placement. SmartClusters are
placed using Physical Compiler's placement engine to produce
complete chip-level placements of 20+ million gates. This provides
the designer a complete and detailed chip-level view needed for
high quality hierarchical floorplan development.
SmartClusters is being augmented with pin-assignment capabilities
already proven in Flexroute. These pin-assignment capabilities
are being extended from the block-level to incorporate a
hierarchical view of the design.
Based on discussions with some of our most demanding customers, we
believe that this approach will save an incremental 1-2 months from
their design implementation schedules.
The Hidden Dragon project does not impact our commitment to deliver an
integrated standard cell router. This project, Route 66, is on
schedule with details to follow soon."
- from "PSS_CA_Mar2001_all_hands_response_final.doc"
So it appears that Chip Architect is going to be replaced by a *real*
hierarchical design planner that has a 25M to 100M gate capacity, that uses
timing "abstracts" and "SmartCluster" hierarchical data compression and
pin-assignment technology from FlexRoute. Oh, and Hidden Dragon doesn't
impact Route 66's delivery date, either! :)
"Did you notice Aart "promising" discounts on Chip Architect to
everyone? :-)"
- Paul Gerlach of Tektronix
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