( SNUG 01 Item 13 ) -------------------------------------------- [ 3/28/01 ]
Subject: Controversial HDL Con'01 Panels, C, Superlog, & Verilog-2000
RIDING THE WAVE: If you're on the ESNUG mailing list, you know I polled
users for extra nasty questions to ask during the "SystemC vs. Cynapps vs.
Superlog vs. Good Olde Verilog/VHDL" panel at HDL Con'01. (FYI -- Goering
reviewed that panel at http://www.eet.com/story/design/OEG20010305S0049 )
After the panel, I asked the audience: "You're a manager leading a design
team to make your company's next chip. It's a typical next chip for your
company -- nothing terribly hard nor easy. Your project starts in 6
months. Which of these methodologies would you use?"
Synopsys SystemC ## 3 (4%)
CynApps CynLib # 2 (3%)
C-Level System Compiler ## 4 (5%)
Co-Design Superlog ############ 22 (28%)
Same Olde Verilog/VHDL ######################## 48 (61%)
It's no surprise that SystemC, CynLibs, C-Level got such low support. What
was surprising was newbie Superlog got 28% of designers willing to take the
technology risk on them. I thought about this for a while and realized that
a number of chip designers blurr Superlog with Verilog 2000. That is, there
are a lot of designers who are enthusiatic about Verilog 2000, and, "Gosh
Golly!, if I can get Verilog 2000 under the Superlog label -- I'll take it!"
Now that Superlog's whipped up all this ethusiasm, it's under painfully
crushing pressure to deliver, and to deliver damn soon. Backlash is a
bitch. Think "Star Wars I: The Phantom Menace"...
"SuperLog (Co-Design Automation - http://www.co-design.com)
* Superset of Verilog2001
* Allows coding in Verilog but provides the headroom to move up in
abstraction and use SuperLog.
* Removes PLI bottleneck by compiling Verilog/Verilog2K, SuperLog,
C/C++/SystemC in a single simulator - SYSTEMSIM.
* Additional constructs targeted for verification planned but not
publicly disclosed yet.
* Extensions to Verilog2K Highlights
- Datatypes similar to C to allow direct sharing of data w/ C
(bit, logic, byte, structures, enum, polymorphism)
- Pointers
- Dynamically sized arrays
- Event Control
always @(written: ), always @(changed: )
continue/break
always_comb, always_latch (implicit sensitivity lists)
- 'process' to send something to the background
- Interface - bundle of wires to pass thru port lists
(Interface is to wires as struct is to variables)
- Parameterizable Text Macros
* Concerns
- SYSTEMSIM simulator performance
Currently a little slower than VCS
Plan equivalent VCS performance in MAY/01
Running SuperLog is faster than Verilog due to higher level
of abstraction.
- Lack of companion tools such as lint and coverage.
- Synthesis support starting with Get2Chip Voltaire product.
Verilog2000:
* IEEE Draft draft available JUN (more likely Fall)
* Enhancement Highlights
- open files increased from 31 -> 2**31
- Multi-dimensional Arrays with full or part selects
- 'generate' statement - similar to VHDL
- 'genvar' variable type used during evaluation of generated
instantiations.
- Enhanced I/O functions
- Re-entrant tasks with 'automatic' keyword
- ANSI-C style port declarations
- Parameter passing by name - only parameters which change
need to be referenced in port instantiations.
- Signed Arithmetic
- ifndef/elsif
- Exponential Operator '**'
- Local parameters 'localparam' keyword - cannot be changed
during instantiation.
- Sensitivity lists: comma separated = 'or'
'@*' eliminates the need to list every single always block
input (automatically includes nets/variables from RHS)
- Attributes '(*' '*)' - remove the need for tools to parse
all comments looking for '//synopsys' for example.
When asked, "What will be the next revision to Verilog beyond
Verilog 2000?", Cliff Cummings (member of IEEE 1364 Verilog Standards
Group) said "SuperLog."
- Jerry Vauk of Sun Microsystems
"SuperLog Tutorial at HDL Con'01
This class was taught mostly by Dave Rich with an intro by Peter Flake.
I would have liked to hear Phil Moorby some but he was not there.
SuperLog is an improvement and an evolution on Verilog. It implements
all of the Verilog-2001 standard (they are fixing some semantic
mismatches now). Backward compatibility with Verilog-95.
Reentrant Tasks - YEAH! Finally! When is Synopsys going to add this
support to VCS???
In Verilog, anything that is passed through a module gets turned into
a wire. In SuperLog if the types match they go through as is.
- Multi-dimensional array support
- packed and unpacked arrays
- Structures and Unions
- Dynamic Types
- Interface definition - This allows a change to the port of a
lower level module without having to change all the wrappers
and modules that the interface goes to before it gets to the
other modules on that interface!!!
*** SuperLog translator to Verilog-95 for a subset of SuperLog has
been released for a while (a year I think) ***
State Machine Syntax - Hierarchical State Machines - I did not
understand this part.
Interface between SuperLog and C++. SuperLog allows 1.) calls to
Verilog tasks from C++ and 2.) Calls to C++ functions and tasks
from Verilog. All that is needed is a simple Superglue file to do
this. Easier to setup than a PLI interface - should be significantly
faster also."
- Dan Joyce of Compaq
"Simon Davidmann is pushing his Superlog simulator as an alternative
to a native Verilog simulator but it does not even run as fast as VCS.
Why would I make the transition to Superlog for questionable language
gains and a loss in simulation speed?"
- Andrew Elms of Nortel Networks
"The philosophy behind SuperLog is to provide a "single language for
hardware, verification, systems." At this point, the language appears
to be focused on modeling as opposed to implementation.
I was expecting to see a description of a modern programming language
that included special constructs to handle hardware-specific issues.
Instead, SuperLog looks very much like Verilog with some C constructs
grafted on top of it. Indeed, one of the early slides states it is a
"superset of Verilog (and Verilog 2000) with the addition of C
programming, system and verification capabilities." While this
approach is comfortable to HDL designers and helps with legacy hardware
designs, it seems that it is quite limiting from the standpoint of HLL
design, true system design and hw/sw design.
Most of the tutorial focused on the new constructs that were available
in SuperLog. There is quite a bit of new stuff and they have provided
a fairly clean path for interoperability with C. However, at its core,
the language is still Verilog and does not have the feel of a powerful
HLL. In addition, I detected a bit of the C++ problem in that there
appear to be multiple ways to perform the same function (leading to
uneccesary complications) and there are a number of constructs that
are non-intuitive, contrary to standard C conventions or are context
specific (again leading to complications and possible confusion.)
Co-Design claims that they have a number of users, but the language is
still under development and they are not planning on releasing it until
the end of the year. Note also that Co-Design has a history of
slipping these dates. To get more information on the language, you
need to sign an NDA. The other aspect of the whole SuperLog package
that was not addressed was tool support. Co-Design claims to have a
simulator for the language (but it is not yet available to the public.)
I find it hard to fathom that SuperLog will gain any traction in the
ASIC community (their target) until they have a good flow to
implementation tools. It seems like Design Compiler support is
critical in this regard. How does this play against the Synopsys
SystemC effort?
Overall, I was pretty disappointed in SuperLog, but it has gotten at
least some good press in the hardware community. How much of this
is the vapor-ware effect is still to be determined."
- an anon engineer
"What does Superlog do which we can't already do with Verilog+PLI+Perl
other than getting me to buy a new simulator & synthesizer?"
- Muzaffer Kal, Consultant
"Superlog seems like a logical step from Verilog. Superlog
doesn't support object-oriented programming features. This
seems foolish to showcase a Verilog-like language without all
of the "marketing bullets" that the other languages have. In
my opinion, Superlog could have killed off all of the other
languages if it had the same features just based on the user
acceptance of Verilog as *the* defacto hardware design language
and we wouldn't have "Spank Janick Bergeron" email threads in
ESNUG. Why wasn't Superlog made object-oriented like the Vera
and Specman E languages?"
- Gregg Lahti of Intel
"I liked having an explicit list of Verilog 2000 features for DC and
VCS from Don Mills. I've been trying to pry the same from Cadence,
so far they've responded with FUD, but no real answers.
In my opinion as soon as VCS and DC support 'generate', Cadence is
going to start losing some customers. I won't use DC features that
aren't simulatable, but I'm willing to act to gain that feature at
least."
- Paul Gerlach of Tektronix
"I can't see us using anything other than Verilog until I can read one
of these formats directly into Design Compiler, and even then it would
be a strectch for us to use something like SystemC. Superlog seems to
be the likely choice just because HUGE investment we have in Verilog."
- an anon engineer
[ The Superlog Tutorial is in "Downloads" at http://www.DeepChip.com ]
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