( SNUG 01 Item 17 ) -------------------------------------------- [ 3/28/01 ]
Subject: Synopsys Module Compiler & Behavioral Compiler
MIXED SYNERGY: Quite a few customers were happy to see Module Compiler
married to Design Compiler; it sort of legitimized MC. On the other hand,
Behavioral Compiler is still seen as a cult tool with its small handfull
of devotees. Marrying BC to SystemC hasn't helped matters here -- because
of the strong anti-C feelings running through the ASIC design community.
"Isn't Module Compiler included into the latest DC to do the arithmetic
stuff? I haven't seen datapath stuff done on embedded chips except in
the CPUs. As for Behavioural Compiler, I don't know of anyone who
uses it."
- an anon engineer
"MC is widely used for datapath. Synopsys used to treat it as a step
child, but lately they've been working very hard to integrate it with
all their other tools. I see real progress there.
BC was a nice idea that never caught, except for a very small group of
users. I guess you could call it a cult."
- Oren Rubinstein of Nvidia
"Module Compiler is good tool. If you know your design and architecture
you can do a better and faster job manually."
- an anon engineer
"MC is useable as it stands now (in fact we're in the process of using
it.) BC is too high-tech. Might as well use C-based methodologies."
- Himanshu Bhatnagar of Conexant
"Session 1: Module Compiler tutorial:
This was a Synopsys run session showing some coding tricks to more
optimally use Module Compiler (MC) with their special language (MCL)
based off of Verilog. Since it was meant for MC users, it was hard
to get much from it as I've never seen the tool.
But the language seems to have constructs for describing datapath
machines in a much more efficient way that Verilog. The idea is
to be able to simply describe several architectures and build them
all, so you can choose one. Whereas to describe the same
architectures in Verilog RTL would be a pain and you wouldn't want
to do more than one.
The features seem to be broken into two classes: pipeline control
structures, and arithmetic features.
Pipeline control structures allow you to specify that this piece
of the pipeline should take 2 clocks, this piece is a feedback
loop so it should take 1 clock, feeding into this that... The tool
is supposed to then choose the best pipeline flop insertion points
The arithmetic features allow extensive use of CSA (carry save
arithmetic or Unresolved arithmetic in Slavin language) for adders
and multipliers. special functions for doing clever things with
the unused lsb input of booth encoders, etc.
MCL is not simulatable but the tool will write out an RTL version
for simulation, even though it's main output is gates.
The users in the session and at lunch seemed to like using it,
though there aren't many users. They view it as a tool, they've
accepted it, use it all the time, and take it for granted.
They wouldn't want to use RTL instead."
- Paul Gerlach of Tektronix
"We're very satisfied with the results Behavioral Compiler is producing
and the progress the tool has made over the last couple of years.
With the latest release we see really good quality of results (DRC,
performance, area, CPU run time) and very good correlation between BC
and the subsequent Design Compiler synthesis steps."
- Johann Bechteler of Siemens AG (Germany)
"We just finished an eval of MC. We have a design that runs at 1.2 GHz.
A good portion of the logic is datapath and MC ate it for lunch."
- an anon LSI engineer
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