( SNUG 99 Item 2 ) ----------------------------------------------- [3/31/99]

   "The presenter gave some interesting statistics for design effort
    at Intel
                  Spec Development   30%
                  Coding             10%
                  Synthesis          15%
                  Design Validation  25%
                  Layout             20%

    I am not sure about the sample size within Intel.  Their initial
    design took 3 months, adding reusability took about 3 weeks, and
    the first re-use of the block took 1 month"

       - Anon
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