( SNUG 99 Item 3 ) ----------------------------------------------- [3/31/99]
The Bigwig's Big Speech
-----------------------
"I think Aart must be renovating his house these days because his big
thing this year was comparing every problem the industry is facing to
various home renovation disasters encountered by 'one of my friends'."
- Paul Chenard of Hewlett-Packard
The SNUG'99 keynote address was given, as it always has been, by Aart de
Geus, the CEO of Synopsys. This year's speech was very odd in that it was
a System-On-A-Chip CEO Talk instead of Aart's usual State of the Synopsys
Union Address. An awful lot was very conspicuous by its absence from
Aart's speech. (For example, *NONE* of the following were mentioned:
Design Compiler, VSS, behavioral synthesis, LMC, Module Compiler, scan
or ATPG, PrimeTime, MOTIVE, libraries, FPGA synthesis, Formality, ECO
Compiler, buying/reselling ViewLogic, Protocol Compiler, nor EPIC tools.)
Here's his speech with all the 'Home Improvement' stories removed.
About 50% of all semiconductors go into PC's, and the next kill apps for
semi's are probably Digital TV, Phones, and Internet appliances. Reuse is
a big topic since design cannot keep up with Moore's Law of gaining 10X
gate density every 6 years. Most systems on a chip (SoC) require both HW
and SW. The design of these IC's are beginning to merge the styles of ASIC
flows and Full Custom flows.
The 3 biggest design challeges are
1. Specifications and Verification
2. Timing and Power Closure
3. IP Reuse
Here are his views on how each will be solved
1) Specs and Verification are a big issue with verification being 50% or
more of the design process. HW/SW co-simulation will help test SoC.
Synopsys has a tool called Eagle that is designed for this.
2) Timing and Power Closure -- Timing is being solved by moving to
physical synthesis. A new tool "Chip Architect" is being released
this year to use placement info in synthesis. Synopsy has purchased
a company called Everest, which deleveloped a top level router tool.
Tool capacity for large chips may be an issue in this area. Power
is being solved by Power Compiler and other related tools.
3) IP reuse is one way to gain productivity. There are 3 kinds of IP
a) Building Block IP - such as DesignWare
b) Complex Commodity IP - this is a difficult model to have
a business around.
c) Star IP - parts like an ARM core that has great IP content.
Synopsys has published the RMM book and has a MORE rating to gauge
the goodness of IP. Some IP companies are having a hard time making
a business model for commodity IP. Synopsys wants the DesignWare
Foundation to always grow over time.
Synosys also has 2 new testbench tools ( VERA and CoverMeter). Radiant
VCS is 3X faster w/ 50% less memory. There are new IP delivery tools
called CoreBuilder & CoreConsultant.
In general, Synopsys 1998 was a $720 M company (3X of its 1993 size) that
invests 22% back into R&D. Revenues broke out by
North America : #################### 55 - 60 %
Europe : ###### 15 - 20 %
Japan : ###### 15 - 20 %
Asia/Pacific : ## 5 - 10 %
In a 1998 "EE Times" survey, Synopsys was ranked #1 for customer support,
Mentor #2, OrCAD #3, Cadence #4. At the bottom of the 12 company list
were Summit Design and IKOS.
"I will forgive not getting to market on time if the reason was to
make the core reuseable."
- Brian Halla, CEO of National Semiconductor (as cited by Aart.)
|
|
