( SNUG 99 Item 19 ) ----------------------------------------------- [3/31/99]
A SEA CHANGE IN DESIGN: Think of a chip world where scan is automatically
built in, no lengthy validation schemes are needed, and troublesome parts
(like a PCI interface) is already built in? Then you're thinking about
the Brave New World of Bigger FPGAs like Vertex (Xilinx), ORCA (Lucent),
and APEX (Altera). They even have their own DesignWare-like libraries
like CoreWare (Altera) and XBLOX (Xilinx) plus some fabs like ChipExpress,
Toshiba, and AMI are offering a quick and easy FPGA-to-ASIC migration path
once your design's debugged. Yea, alot of this is still problematic
(like Altera's flakey PCI part, or the fact that ORCA has *still* yet to
deliver on that 66 Mhz hard macro PCI interface that it promised *two*
years ago, or that 150 ASIC kgates equals 1 Million Vertex gates...)
But, headaches aside, the writing is on the wall and it says 'F-P-G-A'.
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