( SNUG 99 Item 24 ) ----------------------------------------------- [3/31/99]

 The Toshiba Evaluation
 ----------------------

 Tomohisa Shigematsu reported that they took three already finished Toshiba
 designs that had timing closure problems and ran their source Verilog RTL
 through the Chip Architect design flow.  The three designs and results:

                                                   Old Style   Chip Arch
                 Size      Tech   Type     Clock   Iterations  Iterations
                -------  -------  -------  ------  ----------  ----------
    PC chip A     170 k  0.35 um  gt array 66 Mhz     2        1, no viol.
    PC chip B     170 k  0.25 um  std cell 66 mhz     2        1, no viol.
    Multimedia  1,000 k  0.30 um  embedded 50 mhz     5        1, 44 viol.

 The first two designs made their desired timing specs on their first try
 at the Verilog-RTL-to-final-routing through Chip Architect design flow.
 The million gate multimedia chip ran into 44 paths with timing violations
 doing the same flow.

 His flow consisted of three basic parts: 

 1.) To get the block wireload models for each block in a chip:

            Verilog RTL -> CA RTL Estimator -> CA Floorplanner ->
       CA create_placement -eff low -> CA create_wire_load  (makes .db)

 2.) To get each individual block's timing:

                  Verilog RTL -> CA RTL Estimator ->
       CA Floorplan (write_sdf) -> PrimeTime (allocate_budgets)

 3.) The final block stitch together:

  Blk Wire Models + Blk Timing + DC + CA Place -> CND Cell3 or Gate Ensemble


 Tomohisa reported that when they further examined the Chip Architect
 output for the million gate multimedia design, the final-routed paths
 had a timing histogram of

        Chip Architect + 
        DC + Gate Ensemble                       DC + Gate Ensemble
        ------------------                       ------------------

           |           .                    |           .
    number |      *****.             number |           .
      of   | *****     .*              of   |           . 
    paths  |*          . *           paths  |         **.**
           |           . *                  |   ******  .  ****
           |           . *                  |***        .      **
           |           . *                  |           .        **
           ------------+----                ------------+-----------+--
             delay     20 nsec                delay     20          40 nsec

 With a spec of 20 nsec, the worst of the 44 violators cut off at around
 20.96 nsec.  That is, w/ Chip Architect, he had a 4.8 percent Delay Error

     Delay Error == ((Worst Delay - Spec Delay) / Spec Delay) x 100 %

     4.8 percent == (( 20.96 nsec - 20.0 nsec ) / 20.0 nsec) x 100 %

 while his normal flow created a widely flattened histogram with many
 paths having delays going up to roughly to 40 nsec (i.e. with Delay
 Errors going up in the 100 percent range!)