( SNUG 99 Item 41 ) ----------------------------------------------- [3/31/99]
HERE COMES THE SUN: Tirelessly feeding the demands of speed junkies,
along with a number of cycle-based ideas from Viewlogic's Roadrunner
technology, VCS 5.0 now incorporates a front-end parser that analyses
your entire design and performs global optimizations via flattening,
structuring, and more clever ticks to create a faster functional
equivalent of your simulation run. It's called "Radiant" and one
historically reliable source within Synopsys has told me that "with
the radiant in vcs 5.0 we see speedups from 10% to 6x at customer sites,
with a common ranges of 40% to 2x. these numbers are very design
dependant and work equally well for both rtl and gate level designs."
"Improvements Synopsys has made to VCS over the last eight months,
most notably the 5.0 version integrated with Radiant Design
technology, have sped up our simulations around 3X while requiring
no modifications to our Verilog source."
- Alex Silbey of SGI
"The paper was by 2 guys from Gigapixel (www.gigapixel.com) who
had a novel way of driving VCS simulations from a C test bench.
They were designing large graphics engines. They also had a unique
way of specifying the chip such that the drivers, hardware and
software could use the same programming model specification.
Their design environment consisted of dual Pentium II PC's running
Linux and some SUN's for VCS simulations."
- Anon
"By the year 2000, there'll no cycle-based simulators; they'll all be
incorporated within your standard Verilog/VHDL simulator. By the
the year 2001, there will be no Verilog/VHDL simulators, they'll
all be dual language, single kernal, sims like Model Tech's V-system."
- Analyst Gary Smith of Dataquest at DesignCon'99
"VCS : Mark Warren of Synopsys
- Great pitch on new VCS radiant technolgy. Basically VCS
is reducing and moving stuff all around to speed stuff up.
- Lots of great switches for VCS (here is a few)
-xrace-0x11 parses design and then makes a race.out file
during run to give list of possible race condition.
+alwaystrigger parses design and sets up sensitivity list
first to fix intializatioin compile ordering mismatches
dumpvar scripts (free inside $VCS_home/{system}/util
vcat perl to parse (vcat dump1.vcd -scope top.dut.moda)
gives ascii list of signal changes. Very useful on laptop
with no signalscan.
vcdiff compares two dumpvars.
Mark gave lots of code examples of classic Verilog problems with
solutions. He also admitted where VCS fell short."
- Peet James of Qualis Design
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