( SNUG 99 Item 42 ) ----------------------------------------------- [3/31/99]

 HISTORY REPEATS ITSELF:  Towards the end of SNUG'99 there was serious talk
 about doing another design contest like the infamous 'Verilog vs. VHDL'
 contest I held back in SNUG'95.  In it contestants "were given 90 minutes
 using either Verilog or VHDL to create a gate netlist for the fastest fully
 synchronous loadable 9-bit increment-by-3 decrement-by-5 up/down counter
 that generated even parity, carry and borrow."  Of the 9 Verilog designers
 in the contest, only one, Oren Rubenstein, didn't get a final gate level
 netlist because he tried to code a look-ahead parity generator.  Of the 8
 remaining, 3 had netlists that missed on functional test vectors.  (Kurt
 Baty "claims" he "misfiled" his final results.)  The 5 Verilog designers
 who got fully functional gate-level designs were:

      Larry Fiedler     NVidea               3.90 nsec     1147 gates
      Steve Golson      Trilobyte Systems    4.30 nsec     1909 gates
      Howard Landman    HaL Computer         5.49 nsec     1495 gates
      Mark Papamarcos   EDA Associates       5.97 nsec     1180 gates
      Ed Paluch         Paluch & Assoc.      7.85 nsec     1514 gates

 Of the 5 VHDL designers in the contest, *none* of the 5 succeeded in
 getting their VHDL based designs to gates. -- and this caused all sorts
 of reactions in the Verilog vs. VHDL wars.

 What's being kicked around now is doing *another* 90-minute design
 contest next year at SNUG'00.  My problem is exactly *what* would be
 a good, interesting problem for that contest?

   "Yea!  I want another chance to redeem my honor!"

       - Oren Rubinstein of Gigapixel


   "A followup on our lunchtime discussion.  The problem is too little
    time to work on an interesting design.  But how about giving a
    design that needs to go faster and has bugs in it?  This may make
    up for the difficulty in describing complex designs.

    Maybe not bugs, but enhancements, more filter coefficients, more
    memory or something like that.  It would represent some of the
    support issues that happen in real life.

    To be really authentic, the testbench should have bugs too; but
    that may be too hard again."

       - Larry Fiedler of NVidea


   "Those who cannot remember the past are condemned to repeat it."

       - George Santayana, American philosopher, 1863 - 1952