ESNUG Jobs Section

  California - FishTail is seeking AEs based in San Jose, San Diego and Irvine.  Technical
  tasks will include generating and verifying timing exceptions using FishTail's products,
  importing these constraints into major chip-implementation tool suites, resolving any
  integration issues, and obtaining metrics on design QoR improvement.

  Must have 3 years of ASIC design or as an AE, with understanding of the RTL-to-GDSII chip
  implementation flow.  Must have experience with one or more of: Design Compiler, PrimeTime,
  IC Compiler, Blast Fusion, First Encounter.  Experience with SDC, false-paths, multi-cycle
  paths, generated clocks, plus TCL and Perl scripting.  Must have a good understanding of
  synthesizable Verilog, VHDL.  Experience with System Verilog is a plus.  Knowlege of CVS,
  Gnu Gnats bug tracking, and Microsoft Excel a minor plus.

  Prior EDA startup experience is required.  For a candidate with the right skill set and
  a result-oriented, can-do, will-do, failure-is-not-an-option attitude, compensation will
  be a non-issue.

  Interested candidates should e-mail Ajay at ajay29@fishtail-da.com.  No recruiters please.

  Posted: 07/26/2007

   All Jobs Index     Next Job     Place a Job