Begin ( Part 2 of 2 )
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / "One Sheep Farmer's Impressions Of SNUG'98 & IVC/VIUF'98"
_] [_ (plus what 33 other engineers saw there, too.)
by John Cooley
Moderator Of The E-mail Synopsys Users Group (ESNUG)
PART 2: the combined International Verilog Conference (IVC'98)
VHDL International User Forum (VIUF'98)
in Santa Clara, California, March 16th-19th 1998
--------------------------------------------------
The Numbers & First Impressions
-------------------------------
Being one of those Verilog/VHDL "old timers", the first impressions for
the joint OVI/VIUF conferences weren't good. Well, sorta. Why? Because
the first day of the conference were all tutorials for *beginners*.
"VHDL: A Practical Introduction", "Verilog for Synthesis", stuff like
that. So what did this mean? Another day touring San Francisco! But
the downside was that on the last day of the OVI/VIUF they had *eight*
great tutorials on topics like "To IP or Not IP", "Formal Verification",
and "Design For Testability/Built-In Self Testing" -- many given at the
same time! Aaargh! It would have been nice to have some of these
advanced topics taught on the *first* day for us old timers. Argh.
Numbers-wise, this year's attendance of 950 was slightly down from the
preceeding year's 1042 total.
"In purely licence sales (that's not including maintenance fees or
extra waveform viewers or stuff like that), for Fiscal Year 1996
worldwide, VHDL made $60.7 million and Verilog made $113.2 million.
I won't have FY 1997 until the end of this summer."
- EDA Analyst Gary Smith of Dataquest
Oh, yea, remember that pre-IVC/VIUF annoucement I sent out on the ESNUG
mailing list about the Millenium Clocks and that EDAC panel with all
those EDA bigwigs talking about headaches involved with growing a small
EDA into a big one? (It was called "Crossing The Chasm" or something
like that.) It turns out that the Millenium clocks are all wrong because
the new millenium technically starts January 1, 2001 -- not 2000! (Got
6 letters telling me this.) And you can now view the transcripts of that
growing pains panel discussion at www.EDAC.org.
The Two Bigwigs Big Speeches
----------------------------
At OVI/VIUF this year, two keynote addresses were given. Wilf Corrigan,
the CEO of LSI Logic, spoke on Tuesday. Jack Harding, the old CEO of
CCT who then replaced Joe Costello as CEO of Cadence, spoke on Wednesday.
And although I attended both talks, I had a very hard time distinguishing
who said what. This wasn't because I took poor notes -- nope, not that
at all -- it's because they both said almost exactly the same thing!
Essentially, LSI Logic is creeping towards being a design consulting
services house that just happens to be tied to using only one particular
foundry (their own), but that will use most anyone's EDA software.
They also have a lot of their own IP. Here's one of Wilf's slides where
he saw the future going more and more to the "mode" on the far right.
Task - Nature FOUR BUSINESS ENGAGEMENT MODES Task - Content
______ ______ ______ ______ System Design
CREATION | | | | | OEM | | | Architecture
| | | OEM | |______| | LSI | Software/Apps
-------------------------------------------------------------------
DESIGN | | |______| | | | | Micro-Archtctr.
IMPLEMENTATION | OEM | | | | LSI | | LSI | Logic Design
|______| | LSI | | | | | Logic Verif.
-------------------------------------------------------------------
PHYSICAL | | | | | | | | Circuit Design
IMPLEMENTATION | LSI | | LSI | | LSI | | LSI | Layout
|______| |______| |______| |______| Process
Essentially, Cadence has is a design consulting services house that just
happens to be tied to using only one particular set of EDA tools (their
own), but that will use anyone's foundry. They also have a lot of their
own IP. Here's Jack Harding's slide comparing 1985 & 1998. Seem familar?
Electronics Company | Electronics Company
1985 | 1998
--------------------------|---------------------------
INTELLECTUAL PROPERTY |
--------------------------|
DESIGN REALIZATION |
--------------------------| CADENCE
PROCESS MANUFACTURING |
--------------------------|
DISTRUBUTION |
---------------------------|---------------------------
Customer | Customer
If they go the way their CEOs say they're going, can anyone please explain
to me what the essential difference will be between Cadence and LSI Logic
as far as the average chip designer is concerned?
The Conference Itself
---------------------
"Is this a customer? A competitor? A partner? Most people swim in
all of these catagories depending on what day of the week it is."
- Wilf Corrigan, the CEO of LSI Logic
"I PEE, YOU PEE, WE ALL PEE IP": In one of the panel discussions, Gary
Smith, an EDA Analyst at Dataquest related some interesting IP related
stories. "The half-life of soft IP appears to be about 9 months. The
price drops 50 percent every 9 months roughly because many IP companies
are four guys in a garage. I know one IP buyer who paid $250,000 plus
royalties for a soft Universal Serial Bus core because there was only
one supplier for it. A year later, another IP buyer paid just $20,000
(and no royalties) for the same thing because by then twenty other IP
vendors had a soft Universal Serial Bus core."
"The bad thing is that IP doesn't mean anything. The good thing
is that it has become an AltaVista word. It has joined 'sex',
'girls', and 'nude' for high hit-rate keyword searches on the web."
- EDA Analyst Gary Smith of Dataquest
IT'S NOT LOST IN THE TRANSLATION: One of the hottest little tools that
popped up in user surveys about OVI/VIUF'98 was from CompiLogic. They
make an ANSI C to Verilog translator (that runs on either UNIX or NT)
which "supports loops, functions, pointers, structures, arrays, and all
standard C operators." It also claims to support parallelism & pipelining.
(Perhaps to cash in on what they percieve as a booming market, in
January they sold this tool as an alternative behavioral synthesis.)
"By far the most interesting tutorial was the PLI2.0 presentation by
Stuart Sutherland. It gave an excellent overview of the new PLI and
was the only tutorial that I didn't have to glean from -- it had meat
all the way through."
- An anon engineer
"SHOOT THE ENGINEERS AND MANUFACTURE IT!": As a group, we engineers are
a worrisome lot. Because our jobs are so detail oriented and all it
takes is one missed detail becoming the next infamous Pentuim Bug that
makes world news (plus gets us fired), we want to spend forever verifying
*everything*. Problem is we don't have forever as a product market
window. In come the conventional and not-so-conventional verification
EDA tools. The most widely known is Verisity's "Specman" which does all
sorts of complex automatic generation of functional tests based on the
corner cases of external inputs. It also has functional coverage analysis
tools to tell you what you're not functionally testing so far. System
Science has "VERA", but that seems to be only used by Sun Microsystems
because it was developed there. Chronology's "QuickBench" takes a bus
functional model generation approach via waveforms and GUIs. SynaptiCAD's
"TestBencher Pro" does the same thing. The new kid on the block who also
happens to have some *new* technology is 0-in (pronounced "Zero-in").
One word concisely explains what 0-in does: "voodoo". OK, so you might
want more of an explaination than that. Remember back in college learning
to solve all those pain-in-the-ass differential equations for analog
circuits? Remember how you were then mercilessly flung into even more
painfull LaPlace Transform theory? And then, remember how once you
mastered LaPlace Transforms, analog circuit problems were reduced to really
simple algebra problems? The 0-in stuff is JUST LIKE THAT.
As 0-in gobbles up a chip written in Verilog RTL, it does is a detailed
mystical formal-verification-like analysis and it just "knows" via this
voodoo where to place a mess of "checkers" in your design. There are 28
types of checkers. The 10 static checkers monitor stuff like "Unverifiable
Full Case Statements" and "Not possible to verify that mem address will
always be valid". The 18 dynamic checkers monitor stuff like "a tri-state
bus was simultaneously driven by multiple sources", "a mem location was
over-written without being used", or "valid data in a synchronization
register was over-written without being used" -- all time dependant data
usage stuff. A typical 100 kgate design gets about 200 to 500 checkers
generated for it. Next, you feed 0-in all you known functional test
vectors for your design. You know, all that stuff that you hand generated
to test various functions in your design. (Not ATPG stuff, but functional
vectors.) From there, 0-in then figures out your design's legal I/O and
then, by tweaking your I/O, it does directed searches outside of the
space-time continuum that you had established with your hand generated
tests via some occult mumbo-jumbo involving something called "pair-arcs".
(Don't ask. I don't quite know myself.) Anyway if any of this legal I/O
causes your design to do something irresponsible, one of the 200 to 500
checkers will go off warning you. What all this voodoo boils down to is
0-in magically detects *functional* errors in your design that you had
missed with your original hand-generated test suite! It's powerful stuff!
"Any sufficiently advanced technology is virtually indistinguishable
from magic."
- Science Fiction writer Arthur C. Clarke
"Our customers tell us 25 to 75 percent of their time is spent
in verification."
- Jack Harding, the CEO of Cadence
"I believe it was Glen Dearth from Sun Microsystems in his paper
presentation (OVI/VIUF session 7) that said they have a 4:1 ration of
verification to design code. I heard another speaker claim a 2:1
ratio. A friend at Compaq said they were probably 1:1 but growing."
- A Design Engineer from Texas
A LAN BY ANY OTHER NAME: Cashing in on the Web-mania that's been engulfing
110 percent of the non-EE yet technically literate part of the American
public, Synchronicity demonstrated its DesignSync design management
"groupware" that enables distributed teams of design engineers to
collaboratively do rev control along with "user authentication, data
encryption, and compression when sensitive data is in transit" between
design teams. It was sorta like an in-company LAN capable of going
*securely* across inherently unsecured open Internet links.
"We looked at this years ago when I was on RASSP. It's nice to see
someone running with the idea and commercializing it. At work, I
found it hard enough to do rev control on a single disk. I'm sure
it's even harder to do it across an entire company linked up
by the Internet."
- Mike McCollough of Raytheon about Synchronicity's DesignSync
"SHOW ME THE MONEY!": The three questionable in-laws that Synopsys gained
from marrying ViewLogic were the cheesy ViewLogic-developed PC tools,
View's PCB business, and Eagle. Sort of like how modern day Serbia is now
legally considered Yugoslavia even the the old Yugoslavia was much more
than Serbia, the cheesy View PC tools and the PCB business are now what's
legally called ViewLogic. The odd orphan child left out in this game of
corporate musical chairs is Eagle. Without saying the EDA F-word
(frameworks), Eagle makes an "environment" that allows engineers have
outside C models of things like microprocessors running assembly code
interact with a particular ASIC they're designing. (The fancy phrase for
this is "HW/SW co-design". It lets your company's software engineers
test *their* code as it plays with *your* ASIC.) Mentor has a simular
product called "Seamless" and Summit Design is selling "Virtual-CPU" to
do the same thing. But here's where it pays to keep track of how many
engineers attend which tutorials at SNUG: when 298 ASIC design engineers
were given the choice to go to tutorials on either RTL coding tricks,
Formal Verification, and an Intro to Eagle tools, only *nine* engineers
chose the Eagle tutorial. Why the disinterest? Because the biggest
competitor to HW/SW co-verification tools is Verilog. Yup, Verilog.
Intrinsic in Verilog is the PLI, the Programmer's Language Interface,
which allows users to have C models directly interact with ASICs written
in Verilog. And who's the biggest supplier of bus functional C models?
Another division od Synopsys called LMC. Someone tells you HW/SW
co-design tools will be big in the future? I say: "Show me the money!"
"HW/SW co-verification is the larger problem we're facing today."
- Wilf Corrigan, the CEO of LSI Logic
SPICE GIVES ME ULCERS: Ex-Cadence employee and Apteq CEO, Dan FitzPatrick
gave a detailed tutorial with Motorola's Ira Miller about Verilog-A,
Verilog's answer to analog simulation. (Apteq specializes in Verilog-A.)
Not to be left out, the VHDL camp gave a talk on VHDL-AMS (analog VHDL)
with FTL Systems annoucing they's have a VHDL-AMS simulator out by Q3 98.
The one thing both the Verilog and the VHDL fanatics agree on, though,
is that SPICE simulations are waaaaay too slow for real chip design.
"So the question is do you have to wear a tux for formal verification?"
- Ex-Mentor and Gendax (start-up) employee Hal Alles
THE VIEW FROM THE CHEAP SEATS. While 95 percent of the money to be made
in EDA is in high-end, bleeding-edge tools with lots of customer support,
there is a class of poorer engineers with shoestring budgets who must make
cheaper, commodified EDA work. Here's their world in their own words:
"I started working at a small (200 person) company in June. The
company had never done any ASIC or large FPGA work and had no
simulation environment. At the last company I had been using Cadence
tools (Verilog-XL) and SignalScan for debugging, I knew that we
couldn't afford the big boys but we were looking at some honkin' FPGAs
and we needed something. We also had a short schedule & two designers
with VHDL experience and two with Verilog experience, and there wasn't
time to cross train.
"A friend suggested that I check out Model Tech's V-System PLUS which
he saw at DAC and some local Cisco guys were using it. He said he
thought it looked like they had the VHDL to Verilog thing working and
it was pretty inexpensive. So I called them, we also called Viewlogic
since they said their combo thing worked.
"Well to make a long story longer: Model Tech's stuff worked and at
$10K/seat for both Verilog and VHDL its got to be the best deal
in the EDA world. We've been doing FPGA work with it for 4 months
now and co-simulating Verilog and VHDL without any major hitches.
(Well, we have a bunch of .do files to create test configurations,
a TCL interface on the PC would be nice.)
VHDL or
Verilog -> Model Tech -> Synplicity -> Altera MaxPlus2 -> ModelTech
"We're still on a tight budget, and the Verilog guys have been working
in this sort of weird environment: We write modules and work out the
initial bugs with Wellspring's 1000 line version of Veriwell. Then do
the big simulations using the Model Tech stuff. I still wouldn't buy
Veriwell since the free version crashes when you give is a misformed
$display() call.
"Were also working on PCs (Win95 and NT), my biggest beef with Model
Tech is that they haven't kept the PC software up with the UNIX
features (no floating license (eeew dongles!), SmartModels, Tcl)
An editor would be nice but I'm getting use to emacs.
"The Viewlogic guy is still adding up the cost of his stuff, and he has
to be the pushiest saleman in the world. He kept saying he was gonna
provide us the total solution we needed, but when ever we asked whats
the cost he started talking about design flow and how he could help us
all along the way.
- An Anonymous Engineer from a small company designing FPGAs
A NICHE WITHIN A NICHE: Like the Taco Bell chihuahua, there's a whole
family of tiny EDA vendors who are small but well known. They typically
offer niche tools which designers love. InterHDL (which created the
Verilint and VHDLlint syntax/DRC/synthesis checkers, VtoV bidirectional
Verilog/VHDL translation, and the Coverit code coverage tool) annouced
"CheckIt" -- a tool that lets designers check timing & clocking domain
issues at the RTL level in a design. (Very interesting because that type
of checking usually doesn't happen until post-synthesis for most designs.)
The VeriTools chihuahua nipped at the feet of Synopsys/EPIC claiming
that "VeriPower was within 3 to 5 percent accuracy of EPIC's PowerMill,
50 to 100 times faster, and at 1/10th the cost." Systems Science demoed
"PowerFault-IDDQ" that IDs an optimized set of IDDQ test vectors for
your Verilog design. And a whole host of other chihuahuas (like Advanced,
DAI, TransEDA, and Translogic) all yipped about their code coverage tools.
"A fool with a tool is still a fool."
- Glen Abood, Cadence Marketing, introducing his CEO Jack Harding
"If there were no fools, you'd have no customers."
- An overheard wispered reply from another EDA vendor to Glen's quote
JUST THE FAQS, MA'AM, NOTHING BUT THE FAQS: Hats off to Hughes Aircraft
engineer Ben Cohen for his book "VHDL Answers To Frequently Asked
Questions" (Kluwer Academic Publishers). It's *not* for beginners, but
it exhaustively explores all sorts of odd corners to the VHDL language
from multiple perspectives. "How so?", you ask. Ben, my favorite
fellow Lazy Man Of The Moment, wrote his book by compiling thousands of
posts from "comp.lang.vhdl" and its FAQ. It's collective wisdom. Cool!
"I know Paul Estrada. I've partied with Paul Estrada. You, sir, are
no Paul Estrada!"
- overheard being told to Atul Bhalla of 0-in, who was wearing
Paul Estrada's (also of 0-in) name badge to save money on a
conference registration.
"WE'RE NOT DEAD YET" AWARD: Escalade is the only company that bowed out of
the Great ESDA Shootout at the HP Design SuperCon of a few years ago
that's not out of business. They were still alive at OVI/VIUF, but they
don't seem to have much market penetration. (Graphical design entry
users seem to either talk about Summit's Visual HDL or Mentor's Renior.
Escalade's DesignBook just doesn't show up on the radar screen, nor do
ViewLogic's or VeriBest's related tools.) The other company that avoided
the "shootout" (Vista Technology) left the EDA industry altogether.
Speed Electronic went out of business at DAC'97 and i-Logix has switched
to selling non-EDA software developement tools.
Summit Design (which did quite well in the shootout) has the largest
share of the ESDA market with "Visual HDL". And ironically Mentor now
has the second largest market share, yet their ESDA tool came in dead
*last* place in the shootout. Good marketing? Great salesmen? Not
hardly. Mentor killed its ESDA tool "System Architect" and made a
completely new tool (called "Renior") that has the *exact* look & feel
as Summit's "Visual HDL"!
"A talk was given by someone from Compaq about their transition from
UNIX boxes to Compaq compute farms. Good talk. Afterwards, we went
out into the vendor fair to the Compaq booth. When we asked to see
Verilog-XL running on their NT box, the Compaq rep told us 'I would
love to show it to you, but the machine is rebooting right now.'"
- A Design Engineer
MANY HANDS LIGHTEN THE LOAD: Many EDA users expressed an interest in a
computing distribution tool called LSF by Platform Computing. This tool
allows users to schedule and load-share compute runs across mixed UNIX/NT
environments keeping all your computers busy on the job, 24/7. Neat!
"Please feel free to join VHDL International (VI). It's a great
organization. Oh, by the way, by attending this conference, you're
now all automatically members of VI and are now the VHDL Times
mailing list."
- Gabe Moretti, VP at VeriBest and VI bigwig. This comment caused
quite a laugh amoungst the conference attendees because about
70 percent of them are Verilog users.
CADENCE AQUIRES SCOTLAND: With the English failing for centuries to ever
*completely* subdue Scotland (ever see the movie Mel Gibson movie
"Braveheart"?), American dollars have stepped in to do the job quite
readily. Literally, Cadence has approached the Scottish government with
the offer of hiring more than 1,800 emgineers to reside there if Scotland
changes its industrial, academic, & legal infrastructure -- and the Scots
agreed! Apparently Cadence has talked the Scots into creating a sort of
"lawyer free" zone where disputes around IP will be resolved via "private
law" and manditory arbitration. Jack Harding, the CEO of Cadence, has also
expressed that in 6 years, he'd like Cadence to have 10,000 employees,
two-thirds of which will be in the services business. (EE Times 12/15/97)
"What's the sense of selling a piece of IP that has a shelf life of 6
months when it takes a year to negotiate the legal problems around it?"
- Jack Harding, the CEO of Cadence
[ Editor's Note: Last Friday when I was finalizing this Trip Report, at
around 5:00 in the afternoon I recieved an e-mail from a Synopsys
person asking how she could get a copy of this Trip Report. In her
sig it said she was the Assistant to the Deputy General Counsel of
Synopsys. "Lawyers! SYNOPSYS lawyers!" Being a calm, cool, collected
kind of guy, I immediately panicked. I thought to myself: "Oh, shit,
John, *now* what have you done that's got them in an uproar." (Years
ago when I first formed ESNUG, the lovely Synopsys legal department came
after me in an attempt to shut ESNUG down. Ain't EDA fun?) Rather than
panic more, I called her.
me: "Uh. Hi. I saw your e-mail about getting my ESNUG Trip Report.
And you're from the legal department. Anything up?"
her: "Oh, there's nothing wrong. My boss just wanted me to get a copy
of your report. We hear they're quite funny from customers.
We're part of the sales organization you know."
me: [ choking at idea that lawyers being present would *encourage*
anyone to buy anything ] "Oh, OK. You'll get a copy when it's
mass mailed out to my readers. I don't let anyone pre-view my
stuff. You're sure everything's OK?"
her: "Oh, yes. My boss just wants to see it. Everything's OK!"
I hung up the phone and my head was swimming. And for some reason,
Cadence, and Scotland, and "lawyer free zones", and Jack Harding wanting
to hire 6,000 more ASIC designers popped up. "They do allow sheep
there, you know, John...", I thought to myself.
Oh, on a completely unrelated tack, this OVI/VIUF was the first time
I personally got to meet the guy who replaced Joe Costello as the CEO
of Cadence: Jack Harding. And although my initial impressions were
that Jack seemed just like another CEO type -- nothing exceptionally
good nor bad -- now that I've had time to think about it, I think Jack
Harding is a tall, charismatic, powerful man. A natural born leader
with an uncanny insight on how the EDA and consulting businesses work.
A brilliant man! Brilliant! I was standing in the shadow of genius
when I stood next to him. Whoa! :^)
- John Cooley
part-time EDA Consumer Advocate
full-time contract ASIC & FPGA designer
P.S. As always, I like to hear from readers if they thought this two part
Trip Report was useful/fun/accurate. Anything here you you violently
agree/disagree with? Did I miss anything of importance? Tell me!
End ( Part 2 of 2 )
===========================================================================
Trying to figure out a Synopsys bug? Want to hear how 6,000+ other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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