!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / INDUSTRY GADFLY: "Cooley's CDNlive'12 Trip Report"
_] [_ or
One Engineer's report of what happened at the
San Jose Hilton DoubleTree from March 13-14, 2012
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
ATTENDANCE:
For the first 16 years of CDNS history, the company user group went by the
name International Cadence Users (ICU). By 2004, the name was changed to
CDNlive for "better brand recognition". Overall attendance then was:
2006 : : ################################### 1,170
2007 : : ###################################### 1,268
2008 : : ######################### 810
In early 2008, after driving CDNS into the ground, CEO Mike Fister "resigns"
along with 4 other top CDNS execs. But before Fister left, one of his many
legacies was to kill off CDNlive by deciding it would be a "virtual event"
in 2009 -- an online web-only "show" with no actual physical gathering.
2009 : : 0
By early 2009, Lip Bu Tan steps in as the new CDNS CEO and he appoints the
outspoken John Bruggeman as the new Chief Marketing Officer in mid 2009.
Bruggeman revives the Silicon Valley CDNlive 2010 gathering primarily as a
marketing event where users are shown product marketing roadmaps, etc.
2010 : : ################### 611
After Bruggeman cancels CDNlive 2011, he himself is ousted 3 months later.
2011 : : 0
Pankaj Mayor then takes over as VP of Marketing with CDNlive 2012 being yet
again revived
2012 : : ###################### 721
but this time it's returned back to its origins of being more of an actual
user-to-user conference where Cadence customers discuss tool issues, etc.
---- ---- ---- ---- ---- ---- ----
THE THREE KEYNOTES:
This year's San Jose CDNlive had 3 back-to-back bigwig keynotes. Here's
a careful detailed transcription of exactly what each speaker said that was
of any importance to an EDA user:
Cadence CEO Lip Bu Tan: "blah blah blah blah blah blah blah blah"
TSMC US Prez Rick Cassidy: "blah blah blah blah blah blah blah"
ARM VP Tom Lantzsch: "blah blah blah blah blah blah blah blah blah"
As a veteran EDA watcher, I had to say these 3 speeches were amazingly
insightful to me. (And no, I'm not being sarcastic here.)
They were amazing talks because of their secret, untold back stories.
First off, while your typical Big Three or Big Four EDA CEO for the past 20
years has typically been some tech savvy Western (or Westernized) white (or
Indian) engineer who's dabbling in business -- CDNS' Lip Bu Tan is a Chinese
businessman who's dabbling in technology. (Yea, he has a degree in Nuclear
Engineering from M.I.T., but at heart he's a businessman. For example,
while Wally and Aart usually talk on how their tools improve fab yield; Lip
Bu speaks of being an early investor in Pandora and Weibo.com. Second
example, Lip Bu said he talked his two sons into studying EE "because it'll
help them in business.")
The big pluses Lip Bu Tan brings to CDNS is:
- He's a native Chinese speaker and he went to college in China. That
opens CDNS up to a mighty big $$$ market there!
- The guy has connections deep into the Chinese business community.
For example, he knows Morris Chang of TSMC personally!
- Unlike Mike Fister, Lip Bu appears to be running the company long
term instead of doing crazy multi-year FAM deals and then recognizing
the sale in 1 year so he can take CDNS shares private.
Secondly, the rumor was near the end Fister's reign, CDNS VP of Sales
Kevin Bushby paid a visit to Taiwan to shake down TSMC for more money
for CDNS tools. This supposedly poisoned the CDNS-TSMC relationship and
boosted thw SNPS-TSMC relationship for years. (Not good!)
Thirdly, when SNPS bought Virage (with its ARC cores and Artisan libs) that
suddenly screwed over ARM Holdings, PLC -- SNPS and ARM used to sell their
stuff together -- now the entire sales force of the world's largest EDA
company, SNPS, was now suddenly incentivised to sell DW directly *against*
ARM's cores and logic business. (And again, not good for ARM!)
So here's what *I* effectively heard watching those 3 CDNlive'12 keynotes:
Cadence CEO Lip Bu Tan: "Hey, I have amazing connections in China
and I intimately know how business works."
TSMC US Prez Rick Cassidy: "All is forgiven. We now like you CDNS.
We also fear SNPS getting too strong,
so we're going to publically support you
now, too. Here's our 1st 20 nm chip!"
ARM VP Tom Lantzsch: "#%$& you, SNPS! You *&$%-ed with us??? Well,
we've teamed up with CDNS to #%&* you back!!"
These 3 keynotes were just a repeat of what Cadence said earlier "that ARM,
Cadence and TSMC successfully taped out the first Cortex-A15 20 nm test chip
in September 2011. Built on the TSMC N20G process, it includes a single CPU
with 32 KB L1 cache, 512 KB L2 cache, and 2 million instances."
Cadence loves that these were CDNS flows & tools being used -- and NOT SNPS.
---- ---- ---- ---- ---- ---- ----
WORKING LUNCHES:
Instead of the usual everyone-crowd-into-an-exhibit-hall User and R&D mixer,
this year's CDNlive was a little creative. As you walked into the Wednesday
lunch, you were given a map. The map listed 38 12-person tables. And at
each table were specific Cadence R&D people plus empty seats for the users
to join in. For example, Table 10 was TIMING SIGNOFF. Tables 5-6-7 were
CUSTOM/ANALOG. Table 14 was INCISIVE SYS-VERILOG.
That's 1.5 hours to torment the CDNS R&D guys of your choice (they're stuck
at the table and can't leave) plus you get a free lunch! Great idea.
---- ---- ---- ---- ---- ---- ----
THE BEST "PAPERS":
Unlike most other EDA conferences, a "paper" at CDNlive consists only of the
final Powerpoint slides a speaker uses in his/her talk. That is, no actual
formally written/formated paper is written. Out of 95 user "papers" that
were presented, the users voted these as the top 5:
#1 SIV005: Metric-Driven Verification - Going the Extra Mile
by Nancy Pratt of IBM
#2 DIG202: Comprehensive QRC/ETS solutions for 28 nm Timing Signoff
by Arvind NV of Texas Instruments
#3 DIG101: Quantifying impact of Double Patterning for 20 and 14 nm
by Lars Liebmann of IBM
#4 SYS103: Fast Processor Models for SystemC Virtual Platforms
by Larry Lapides of Imperas
#5 CUS001: LDE Aware Design Flow Automation
by Erik Wanta of Freescale
I was a bit surprised a design data management (on ePlanner and eManager)
was #1 user paper this year; but with the recent Extreme GoldTime and
Magma Tekton aquisitions by SNPS, I was not surprised to see Cadence ETS
(CDNS's version of PrimeTime) grabbing the #2 spot. (Monopolies scare
users; they want alternatives.) Digital and full custom took #3 and #5;
two niches CDNS is strong in. Non-CDNS SystemC by Imperas as #4 was
also unexpected, too!
---- ---- ---- ---- ---- ---- ----
TECH NUGGETS & RUMORS:
Here's the Silicon Valley CDNlive'12 user presentations that I thought
were "interesting" for one reason or another.
For digital P&R, some impressive logos liked Azuro CCOPT:
- (HPA102) was Kirin Jayanthi of TI Austin about how they used
CDNS RTL Compiler, FE, and then Encounter P&R along with the
newly acquired Azuro CCOPT CTS tool. TI made a dual-CPU ARM
Cortex-A15 with 2 MB L2 in std cell 28 nm low power at 2.0 Ghz.
Some RTL Compiler Physical and its physical aware scan stitching.
Mostly focused on P&R with a emphasis on clock nets, OCV, and
Azuro CCOPT CTS, and plus power optimization. (I forgot to
ask if Texas Instruments Austin used PrimeTime or Cadence ETS
for signoff; and Calibre or Cadence PVS for DRC.)
- (HPA103) was Arthur Abnous of Broadcom discussing manual useful
skew for slack redistribution and Azuro CCOpt. CDNS claims
10% better design performance and total power, 30% reduction in
clock power and area, 30% reduction in IR Drop. Also discussed
datapath opto, with 8% improvements. Margining for AOCV.
- (HPA101) was Ranjit Loboprabhu of Netronome discussing power
optimization using a standard CTS flow vs. Azuro CCOpt CTS;
"CCOpt gave 29% power savings and a 10% improvement in timing"
plus "adding Clock Gating resulted in a 11% power savings."
And the other digital tools got good coverage:
- (DIG002) was Jerome Albert of Applied Micro discussing his
use of Conformal Constraint Designer (CCD) and touched on
I/O timing, clock definition and hierarchical checks. Did
rules checking with 200+ rules covered by CCD.
- (DIG102) was Krishna Kumar Gundavarapu of Cisco on using
Cadence EDI System (i.e. First Encounter) to do "automated
floorplan synthesis" and feasibility of a chip. He got a
realistic top-level floorplan with real/dummy memories.
- (DIG202) was Arvind NV of Texas Instruments on Cadence ETS
and QRC. For ETS, these slides cover OCV, GBA, GBA-2, PBA,
AOCV, crosstalk delay accuracy, SI analysis, crosstalk slew.
For QRC 11.1, binary parasitics, ctotal accuracy, NDR nets,
coupling caps. Runtime & mem benchmarks for ETS-SI and QRC.
In light of Extreme Goldtime and Magma Tekton joining Aart's
PrimeTime monopoly, this paper was good news. Lots of good
tech meat. Easy to see why it was voted #2 best paper.
- (DIG108) was Ranjit Loboprabhu of Netronome discussing DFT,
boundry scan, MBIST, LBIST, full scan, compressed scan, PTAM,
ATPG, etc, in Cadence RTL Compiler and Encounter Test in a
widely parallel and distributed mode.
I was bummed that I missed:
- (DIG104) a presentation by Jason Redgrave of Imagination Tech
on doing a bottom-up DFT insertion with Cadence RTL Compiler
in a hierarchical Encounter P&R flow.
For Virtuoso, AMS, full custom:
- (CUS201) had Pei Yao of GlobalFoundries gave the detailed 28 nm
production-ready AMS GloFlo reference flow. (I'm curious due the
lingering TSMC 28 nm production problems in ESNUG 503 #5. I
figure if GloFlo can do 28 nm AMS, GloFlo 28 nm digital would
be trivial.) Talk covered mostly CDNS for layout, but also
mentoned Solido, Helic, Lorentz, SNPS, MENT and Apache.
- (CUS003) was Malcolm Stevens of Cortina Systems discussing
using CDNS Interactive Physical Verification System (IPVS)
inside Virtuoso to fix LDE & DRC issues early in 28 nm flows.
- (CUS002) was Eduard Raines of Analog Devices giving his
impressions of Circuit Prospector for custom design reuse.
Migrates a design from 5 V to 3.3 V. Detailed SKILL, too.
- (CUS007) was Julia Perez of Freescale giving her impressions
of the Fluid Guard Rings instantiator in Virtuoso.
- (MSL201) was Sorin Dobre of Qualcomm discussing CPF 2.0 and
UPF 2.0 and hierarchical Conformal Low Power use.
I was bummed that I missed:
- (CUS001) was Erik Wanta of Freescale giving a talk on Layout
Dependent Effects. He spoke about new CDNS Virtuoso "LDE
parameter extraction and backannotation flow" and what he
found using it on a real design using TSMC 28 nm PDK.
- (CUS005) was Richard Shi of Orora Design chatting up his
Arana which automatically extracts "intelligent behavioral
models" from circuit netlist. Claims 100x - 1000x faster
than SPICE. Orora showed Arana at DAC'04 and DAC'09.
For OVM, UVM, assertions, verification:
- (SIV001) where Lina Lin and Flora Gao of LSI did a "best
practices" of assertion based verification. Many OVM tips!
Lina also did (SIV003) on customized Metric-Driven Verification
plus a web-based regression report system.
- (SIV101) was Jain Sakar and Thinh Ngo of Freescale's overview
of concurrent coverage-driven verification. MDV.
- (SIV102) was Saeed Shamshiri and Michael Hsieh of Marvell doing
a really complex formal verification (that I didn't quite fully
understand) of a messy design. Assertions, Parameterized, Code
reuse & property reuse, Equivalence checking, Divide & Conquer.
For SystemC, TLM-2.0, IP-XACT, and virtual crap:
- (SYS002) was David Beal of Xilinx giving an overview of all
the SystemC, TLM-2.0, IP-XACT stuff to create a virtual Xilinx
Zynq-7000 EPP model. Minor mention of C-to-RTL synthesis.
Papers by CADENCE that caught my eye:
- (DIG005) was Simon Wong of OmniVision going into detail about
the smart way to use Conformal LEC. Simon now works at CDNS.
Regardless, it's detailed HOW TO doing LEC with either Design
Compiler or CDNS RTL Compiler output. Good tech meat here.
- (DIG106) was Ankush Sood of Cadence discussing hierachical flows
with CDNS RTL Compiler. ILMs, partitioning, assembly, etc.
Again, instead of CDNS marketing pitches and roadmaps that Bruggeman had
done at the CDNlive'10, this year's CDNlive'12 was more user-to-user talks.
I liked the feel of users close together in small groups vs. they being
in big rooms with microphones. It helped users speak up right away about
a topic vs. waiting for their turn at the mic.
---- ---- ---- ---- ---- ---- ----
MISSING TOOLS & MISSING PEOPLE:
Here's the conspicious tools and people whom I never saw at CDNlive'12:
- I couldn't find any direct Palladium papers, but I did find (SYS201)
by Juergen Jaeger of Cadence on FPGA-based prototyping with "ASIC
to FPGA memory conversion, fast synthesis (~30 M gates/h), automatic
multi-FPGA partitioning (~20 M gates/h)" then use "Palladium to debug
the functionality." Hmmm....
- Even though CDNS paid $315 million for Denali, I failed to find
any Denali-based memory or Verification IP papers.
- And in line with the Specman "e" controversy that's been brewing
in ESNUG 501 #2 & 500 #3, I found no papers discussing Specman "e"
in any serious way.
- Before I got to CDNlive'12, I heard a rumor that Cadence had laid
off 40% of its C-to-RTL synthesis group. In line with that rumor,
there was no significant coverage of their C-to-Silicon Compiler at
this CDNlive. Nor was Michael McNamara, the "VP and GM of the
C-to-Silicon Compiler group" anywhere I was.
- Also Chi-Ping Hsu, CDNS Senior VP of R&D (*the* major bigwig at
Cadence after Lip Bu Tan) and Charlie Huang, the Senior VP of
Worldwide Sales & Field Operations were both noticeably missing.
  
---- ---- ---- ---- ---- ---- ----
EXHIBIT HALL:
The following companies exhibited at CDNlive'12: ARM, TSMC, GlobalFoundries,
Samsung, IBM, ClioSoft, Lorentz, TowerJazz, Ansys (Apache), ChipEstimate,
CLK Design, CST, EDAxact, EMA, IC Manage, Imera, Methodics, Nimbic, Orora,
OpenText, SkillCAD, Sonics, and SpringSoft.
 
I liked that Lip Bu Tan showed up unexpectedly with a beer at the Monday
night CDNS Partner Expo. He's a refreshing change from the days of when
CTO Ted Vucurevich was "stuck" hosting CDNlive'08 while CEO Mike Fister
*literally* phoned in his CDNlive'08 keynote. (I'm not making this up.)
Industry observer Peggy Aycinena wrote at the time: "What's the difference
between the CTO and the CEO? The CEO's the one who never shows up for
speaking engagements and doesn't give a rat's ass if the CTO's dignity is
sacrificed in the process."
Compared to before, Lip Bu Tan is a welcome change.
- John Cooley
DeepChip.com Holliston, MA
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
|
|
