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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2013"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
You might want to print out a hardcopy of this as an unofficial guide to the
Austin DAC exhibit floor. List ranked in order of importance.
PRIMETIME ALTERNATIVES
1.) This year's #1 "MUST SEE" is the new Cadence Tempus STA tool that's
taking a run at Aart's PrimeTime monopoly. I call it the Revenge of
Rajeev; because instead of it being yet-another-CDNS-R&D-developed
tool -- it was spearheaded by ex-Magma SPICE folk in CDNS who know
the ugly crosstalk & SI side of STA. 50 M inst design in PrimeTime
took 8.5 hours on 8 CPUs; Tempus did it in 58 min on 32 CPUs. The
20+ year old PT can't do multiple machines; Tempus written that way
from the beginning. Tempus is NOT a repackaging of old Cadence ETS
STA; it's NEW code. New path-based analysis (PBA) engine instead of
old graph-based stuff. 100's M cell capacity. No SNPS-proprietary
Parametric OCV (POCV), instead TSMC's open Statistical OCV (SOCV).
Tempus does full flat, hierarchical, incremental timing analysis.
Big question has/will TSMC certify Tempus for golden signoff STA?
TI uses it. (booth 2214) Ask Ruben Molina. Freebie: Denali tix
Aart's people are countering CDNS Tempus by showing a PrimeTime that
now reads LEF/DEF and works with ICC MPI for "physically-aware
signoff-driven ECO guidance". "Highly-congested, low power 20 nm,
and latch-based cores now get fast timing closure." SNPS says 40%
of most design cycles is spent in timing ECOs. And PT SIG meets on
DAC Monday. (booth 947) Ask for Bernie Mortell. Freebie: stylus
EMULATION / ACCELERATION / PROTOTYPING
2.) Wally and Greg shocked the EDA world when 11 months ago they said
their Mentor Veloce 2 will pass Cadence Palladium by end-of-year.
(ESNUG 510 #7). Snooping I found out that Veloce 2 has roughly
the same cost-per-gate, same compile time, same debug visibility
as Palladium. "But for identical capacity it's 1/4 the size and
uses 1/4 the power and cooling Palladium does. Veloce Codelink
runs software debug 20X faster than Palladium's JTAG probes.
Veloce Testbench Xpress ~4X faster simulation acceleration than
Palladium." Veloce 2 even has a 2 billion gate box installed!
Broadcom, Mitsubishi, NXP, ST, Trident, ZTE, HiSilicon uses it.
(booth 2046) Ask for Jim Kenney. Freebie: stuffed bat
Cadence Palladium XP will have functional coverage, dynamic power
analysis, full ICE 10x speed improvement into Mhz range without loss
of analysis data. And their Virtual System Platform plus Palladium
boots Linux 60x faster vs. Palladium alone. TI, Broadcom, AMD,
Freescale, Samsung, LeCroy, Sharp, PMC all use Palladium XP boxes.
(booth 2214) Ask Frank Schirrmeister. Freebie: Denali party tix
Synopsys EVE ZeBu and SNPS Synplicity HAPS and SNPS ChipIt all
play in acceleration/emulation/protyping. Unsure if any of them
at this DAC. (booth 947) Ask Joachim Kunkel. Freebie: stylus
Cadence Rapid Prototyping Platform is a FPGA-based prototyper to
model your ASIC in FPGAs. Fast time-to-functionality. Automatic
ASIC-to-FPGA memory conversion, clock tree transformation, and
pre-P&R model validation. "quick bring up is in 4-6 weeks instead
of 3-4 months." Freescale, Nvidia, Hitachi, ARM uses RPP.
(booth 2214) Ask for Juergen Jaeger. Freebie: Denali party tix
Aldec HES is emulation SW for off-the-shelf FPGA prototyping boards
or custom in-house FPGA boards. Automatic partitioning, ASIC-to-FPGA
clock conversion, static/dynamic probes, memory viewer, triggering,
HW breakpoints. New HES-7's plus backplane gives 96M ASIC gates
with Xilinx Virtex-7's. Fuji-Xerox, Sandia, Textron uses Aldec.
(booth 2225) Ask for Bill Tomas. Freebie: steel water bottle
Flexras Wasga Compiler does timing driven partitioning for FPGA-based
rapid prototyping of ASICs. Virtex-7. Wasga Architect input HDL
design, interfaces, speed. Output a custom FPGA-based board netlist.
(booth 1324) Ask for Matthieu Tuna. Freebie: none
Dini Group says "Quad V7 is here". (booth 818) Ask for Mike Dini.
DIGITAL P&R
3.) With rumors that Aart is about to sue Atoptech over POCV licensing,
I'll naturally be at the Atop booth asking "Why does Synopsys see you
as a threat?" Atoptech Aprisa rev 13.02 is now certified TSMC 16 nm
FinFET. Color-aware double patterning. Fast physically-aware ECOs.
Timing closure based on sign-off timing. CTS. Virtual Flat stuff
and In-Hierarchy Optimization. Oh, and as a sweet public F.U. to
Aart's lawyers, Atoptech is bailing on SNPS POCV and going all-in on
TSMC's open Statistical On-Chip Variation (SOCV) instead! OUCH!!!
Mellanox, PMC-Sierra, Broadcom, Clariphy, PLX, Xilinx, Cypress users.
Now new rumor is Cadence told Atop "NFW" to a $300 M buyout price.
(booth 2033) Ask for Eric Thune. Freebie: flying pig toy
Cadence Encounter Digital will be doing:
- combined physical-aware synthesis and optimization "for faster
timing closure" and "CCOpt (Azuro) that optimizes clocks and
data-path simultaneously" and claiming 10% faster chips.
- floorplanning now "handles designs of 100 million instances".
- "Silicon-proven, foundry-certified 20-nm flow with a unique
correct-by-construction double-patterning" and ECOs and area.
- Hey, isn't our GigaOpt physical synthesis optimization engine
really super-duper kick ass!
Last year, EDI had first/only ARM Cortex A15 tapeout at TSMC 20 nm.
This year, EDI has first/only ARM Cortex A57 tapeout at TSMC 16 nm
FinFET! -- the CDNS/ARM way of saying "%$#^ you, SNPS!" Samsung,
ST Micro, TI, Fujitsu, Spreadtrum, Marvell, Renesas uses CDNS EDI.
(booth 1930) Ask for Rahul Deokar. Freebie: Denali party tickets
Mentor Olympus-SoC with be showing for 20/16/14 nm:
- Concurrent PPA optimization, proprietary density mgmt and RC
prediction with single global routing engine.
- FinFET, double patterning, native coloring, global conflict
resolution, "auto fix double patterning violations during
routing" and "DP prevention during placement using groups
and spacing rules, color anchoring, pre-coloring, coloring-
aware extraction, and DRC/DP Calibre signoff inside Olympus".
- Pseudo flat flow does best of flat and hierarchical flows.
- Does MCMM, CTS, proprietary congestion mitigation.
Will have Nvidia, ST, and Ostendo talking about best area, Mhz and
fast TAT in their booth. Floorplanner does auto macro placement.
(booth 2046) Ask for Sudhakar Jilla. Freebie: stuffed bat
Synopsys IC Compiler will have IC Validator (DRC) handling double
patterning at "all nodes" and new concurrent clock/data capability.
(booth 947) Ask for Mark Bollar. Freebie: stylus
SPICE & AMS
4.) With Lip-bu Tan suing them, you betcha I'm going straight to the BDA
booth to see what new trouble they're up to! BDA Analog FastSPICE
identical to Spectre/HSPICE but 5x to 10x faster. Foundry certified
to 20 nm. Does 10+ M elements. Full-spectrum device noise analysis.
Mixed multithreading/multicore parallel support for repeated runs.
NEW! -- BDA Analog Characterization Environment (ACE) completely
replaces Virtuoso ADE-XL for analog characterization runs. Has the
crazy idea of "Analog regressions, imagine that" plus angering CDNS.
NEW! -- BDA AFS Mega for fast & accurate SPICE runs of mega arrays
like memories. Supports DC, transient, transient with dynamic temp,
alters, sweeps, and Monte Carlo. TSMC selected AFS Mega for 16-nm
FinFET memory verification. No wonder Cadence is trying to ding BDA.
(booth 2025) Ask for Roshan D'sa or Pi. Freebie: disco pen
ProPlus NanoSpice does big ass capacity parallel SPICE. Did 576 M
element full-chip DRAM, 50.5 M transistor SRAM and 67 M element post-
layout SRAM. "10x+ speedup over other parallel SPICE on long runs."
(booth 1525) Ask for Amit Nanda. Freebie: wireless mouse
Solido Variation Designer does variation-aware custom IC design for
PVT corner analysis, 3-6 sigma Monte Carlo and variation debug. Big
thing is it cuts waaaaaaaaay down on how many SPICE runs you need.
Interesting back-and-forth with Cadence on this in ESNUG 524 #5.
Tool is certified by TSMC and GlobalFoundries, and is integrated
with Synopsys HSPICE/HSIM/FineSim/XA, Cadence Spectre/APS, Mentor
Eldo, Agilent GoldenGate and BDA AFS. Has TSMC 16nm/TMI2 support.
(booth 1915) Ask for Amit Gupta. Freebie: 3D FinFET model
MunEDA WiCkeD High-Sigma calculates worst-case conditions for local
random variation by worst-case analysis (FORM), estimates high-sigma
quantiles and distribution shape for non-linear spec boundaries by
importance sampling. "Increased capacity." Samsung, SK Hynix,
STMicroelectronics, Fraunhofer, Sanyo, Toshiba, and Altera users.
(booth 1725) Ask for Andreas Ripp. Freebie: coffee mug
ProPlus NanoYield does variation analysis on yield vs. PPA trade-off.
High Sigma Monte Carlo. Licensed from IBM five years ago. Now has
fast PVT for analog (load and RC corners) and mem/std cell char,
with 4x-20x speed-up over using full factorial PVT. SMIC user.
(booth 1525) Ask for Amit Nanda. Freebie: wireless mouse
LibTech YieldOpt does worst/best process conditions for std cells and
IOs under any variation scenario. Async threshold logic support.
(booth 1443) Ask for Mehmet Cirit. Freebie: none
Cadence AMS Designer does CPF AMS sim, automated analog behavioral
model generation and validation. Create schematic view of your
behavioral model in their GUI and then validate it automatically.
Low power by power-gating and dynamic voltage frequency scaling.
(booth 1930) Ask Sathishkumar Balasubramanian. Freebie: party tix
Pulsic Unity Analog Router is a "guided, intuitive, step-by-step
interactive or fully-automatic flow for Analog routing (NOT Custom,
but true Analog!) with a built-in DRC checker." Renesas uses it.
Pulsic Unity Chip Planner is a hierarchical full chip black box
floorplanner with extraction, incremental ECOs, top level block & pin
placement, legalization and optimization. Top level signal planner
with 'push down' capability. LEF/DEF, OA, .lib, SDC, SPF/DSPF.
(booth 2243) Ask Lee Williams. Freebie: keychain flashlights
Symica AMS Design Suite is like Tanner EDA but has only two years
in business and it's based in Kiev. "007: From Russia With Love"
(booth 1619) Ask Sergey Makarov or Vlad Potanin. Freebie: none
Infiniscale IClys does Monte Carlo to 50X, and High-Sigma analysis
1000,000X and variability analysis of well proximity effects.
(booth 419) Ask for Yoann Courant. Freebie: none
NEW! -- ClioSoft SOS viaADS does design data management with the
Agilent ADS & GoldenGate. Enterprise-wide revision control, design
management and multi-site team collaboration support for Agilent ADS.
(booth 2125) Ask for Karim Khalfan. Freebie: racing cap
Cadence Virtuoso Liberate is their new name for the Altos cell lib
characterizer. Does electrical cell views for timing (NLDM), power
(NLPM) and signal integrity. CCS, ECSM, CCSN, and ECSMN. Runs well
with Spectre. Rivals are Liberty NCX, SiliconSmart, Mentor Kronos.
(booth 1930) Ask for Ahmed Elzeftawi. Freebie: Denali party tix
NEW! -- G-Analog GChar does std cell characterization that 50X faster
because is runs on GPU's. "SPICE accurate." Monte Carlo, OCV. Was
written by one of the Nassda founders who was from Synopsys and EPIC.
(booth 1827) Ask for Jeff Tuan. Freebie: candy
LibTech LibChar does std cell, IO, SRAM characterization and modeling.
Automatic configuration, threshold logic modeling for async designs.
(booth 1443) Ask for Mehmet Cirit. Freebie: none
Cadence QRC Extraction parasitic extraction does "gate, RF, analog,
mixed-signal, custom digital, and LCD-TFT." Competes with Star-RCXT
and Calibre-XRC. CDNS QRC does "RLCK extraction, 16/14 nm modeling,
multi-corner and statistical extraction, distributed processing,
netlist reduction, substrate noise extraction (SNA), inductance
extraction" and works well with Encounter Digital or Virtuoso.
(booth 1930) Ask for Hitendra Divecha. Freebie: Denali party tix
EDXACT Jivaro does RLCK reduction of parasitics, generated by post-
layout extraction. Cuts sim time and mem footprint. Dynamically
loaded library into Agilent's GoldenGate does reduction on the fly.
Cuts inductance and mutual inductance. Mediatek, TSMC are users.
(booth 814) Ask for Mathias Silvant. Freebie: pens
Tela Innovations sells Tela Optimizer which cuts leakage power
in 90 nm to 28 nm. (booth 1815) Ask for Scott Becker.
Integrand EMX is a 3D EM simulator for modeling on-chip passives
and interconnect and RF. TSMC, GloFlo, UMC, IBM, Samsung, Huawei users.
(booth 1926) Ask for Sharad Kapur. Freebie: none
IROC Tech TFIT predicts soft error FIT rate on CMOS digital cells.
(booth 1738) Ask for Olivier Lauzeral. Freebie: none
Cadence Litho Physical Analyzer (LPA) does DFM analysis & talks with
Encounter NanoRoute and the Virtuoso Custom router to incrementally
and surgically fix litho hotspots. It even works with SNPS ICC.
(booth 1930) Ask for Manoj Chacko. Freebie: Denali party tix
RTL SIMULATORS
5.) Rocketick RocketSim loads your Verilog source into 100's of GPUs and
runs as a co-sim to Cadence NC-Sim, Synopsys VCS, Mentor Questa.
Made news in ESNUG 523 #4 when it made VCS 23X faster with 80% less
memory. Rumor is Synopsys had an internal GPU project for CUDA VCS
but it only did gates. RocketSim does both gate and RTL for VCS.
Scales to multiple-GPUs. "Compile 1 billion-gate design in 2 hours"
4-state-logic for X. (booth 1225) Ask Uri Tal. Freebie: USB keys
Cadence Incisive does "UVM for System Verilog, SystemC, Specman 'e',
mixed-signal and low-power. 30% speed-up. Better setup and runtime
for accurate RTL low-power sims. Updated coverage analysis. New
low-power debug, performance, and extension of support to 1801/UPF.
(booth 2214) Ask Terry Lyons. Freebie: Denali party tickets
Synopsys VCS and Mentor Questa compete in general RTL/gate simulators,
but unsure if they're showing anything new at this DAC.
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
Now does constrained and coverage-driven randomization and functional
coverage by OS-VVM for VHDL designers. SynthWorks somehow involved.
(booth 2225) Ask for Bill Tomas. Freebie: water bottles
Amiq DVT Eclipse IDE provides IDE for design and verification
languages like "e", System Verilog, VHDL. Visual C like stuff.
Capacity. "Took one customer's 15 M lines of code, no problem."
(booth 2435) Ask for Cristian Amitroaie. Freebie: none
WinterLogic Z01X does gate and RTL fault simulation. Functional
IDDQ testing is new. Competes vs. Synopsys Certitude. Nvidia,
Freescale. (booth 2034) Ask for Jason Campbell. Freebie: game
Verific sells System Verilog and VHDL parsers with C++ interfaces to
EDA tool developers. Perl interface. Parsers for UPF, PSL, EDIF.
New SQL interface so you can store, retrieve, and query System
Verilog and VHDL designs thru language independent SQL commands.
Synopsys, Magma, Apache, EVE, SpringSoft, IBM, Infineon, NXP user
(booth 2141) Ask for Michiel Ligthart. Freebie: stuffed giraffe
SYNTHESIS
6.) Oasys RealTime Explorer is a design estimation tool that works a lot
like the olde First Encounter or the more recent Synopsys DC Explorer
in that it goes from RTL super-fast to placed-gates so the RTL design
guys get quick feedback about congestion, timing, power, constraints
EARLY IN THE DESIGN CYCLE. Cuts RTL <-> P&R iterations. Verilog,
VHDL, System Verilog, MCMM synthesis, DFT, UPF/CPF low power design.
"Done 22 nm tape-outs!" Intel, Broadcom, TI, Juniper, Qualcomm.
Anyone using Xilinx Vivado tools use RealTime Explorer. Last week
Joe Costello, Intel Capital, Xilinx did another round of funding.
NEW! -- RealTime Floorplan Compiler takes Verilog/VHDL RTL for entire
chip to a super-quick floorplan that "meets timing, power, area and
physical constraints". "floorplaning of 4-6 weeks down to 2 days!"
(booth 1231) Ask for Scott Seaton. Freebie: pen
Cadence RTL Compiler does physical aware and low power optimized
synthesis of RTL to placed-gates. Competes vs. Design Compiler.
PAM - Physical Aware Mapping: Improve timing by considering
real wire delays before mapping to generic gates
PAS - Physical Aware Structuring: Decrease congestion through
optimized structuring including MUX decoding
PAR - Physical Aware Restructuring: Tree rebalancing for
improved timing & cleaner placement
PA-DFT - Physical Aware DFT: Scan chain reordering and ATPG
congestion spreading
Used by TI, IBM, Freescale, ST, Canon, Cisco, Apple in conjunction
with Synopsys Design Compiler -- as a dual flow -- choice is good!
(booth 2214) Ask for David Stratman. Freebie: Denali party tix
Synopsys has "cool demo" DC Explorer and Design Compiler Graphical.
RTL design exploration, floorplanning, and advanced RTL debugging.
(booth 947) Ask for Gal Hasson. Freebie: stylus
BUGHUNTERS
7.) Through some accidental data, a few months ago I discovered that
there was a strong user interest in Jasper's Secure Datapath App
such that I called up Kathryn Kranen to have her guys write-up
its case study in ESNUG 524 #3. It FORMALLY determines whether it
is possible to leak secure data by unexpected paths in your chip.
That's BIG! (booth 2346) Ask Ziyad Hanna. Freebie: tote bag
NEW! -- Mentor Questa Cache Coherency formally checks "complex
fabric interconnect and advanced cache coherency". It generates
bus traffic to verify interconnect function and performance.
Covers all cache states and transitions to verify coherency
performance." (booth 2046) Ask Mark Olen. Freebie: stuffed bat
Undaunted by colossal failures all the EDA companies experienced
last year trying to lock EDA users into their own proprietary tool
Clouds, this year OneSpin 360 is now renting equivancy-checking
and property-checking as pay-per-use on their own Cloud. "Once
more unto the breach! Or close up the wall with our EDA dead!"
(booth 846) Ask Raik Brinkmann. Freebie: Cloud pep talk
Questa Automatic Formal does "faster, smarter verification with
an emphasis this DAC on assertion generation, X-state and reset
verification; and clock/power domain convergence verification."
Alcatel-Lucent, Mediatek, AMD, Qualcomm, Xilinx, Infineon users.
Oh, and it's automatic, too! (booth 2046) Ask Roger Sabbagh.
Atrenta BugScope does assertion synthesis and this year it will
"check unproven CDC assertions; each unproven CDC assumption
is automatically checked against the regression." Also new
"each synthesized property is NOT required to be classified by
the designer before being used" and "Which IP is NOT verified
enough?" and "Am I configuring IP correctly?" TI, Marvell,
QLogic, IDT. (booth 1847) Ask Yunshan Zhu. Freebie: pen
Avery PSYN does assertion synthesis for baseline verification metrics.
Extracts microarchitectures. "Over 15 microarchitecture functions
and 60 assertions, cover properties, and covergroups supported."
Now supports pragmas. Rival to BugScope and Jasper. Hitachi uses it.
(booth 1835) Ask for Chris Browy. Freebie: LED flashlight
Atrenta SpyGlass Constraints does formal false path, MCP, and clock
intent verification, SDC validation, SDC equivalence check so your
constraints are in sync with evolving design/SDCs and incremental
SDC generation. A big selling tool. Renesas, Fujitsu, TI, ST, ARM.
(booth 1847) Ask for Ramesh Dewangan. Freebie: pen
Atrenta SpyGlass CDC does "protocol independent CDC checks for
control, data, and reset signals" and "CDC for data loss, glitch
hazards, data stability, re-convergence, and FIFO issues." This
year new hierarchy gives it 10X speedup and 5X better memory use.
It signed off a 1.4 billion gate design recently. Broadcom, LSI,
Qualcomm, TI, ST, Panasonic, Infineon, Ericsson, Cisco uses it.
(booth 1847) Ask for Ramesh Dewangan. Freebie: pen
NEW! -- Ausdia Timevision-CDC does "block/fullchip CDC analysis on
RTL or gates using SDC constraints only -- so it can verify your
actual clock groups as being CDC-safe. Chips of 20 M to 500 M
inst with 1000 clocks in 8 hours. Implied multimode screening to
suppress structural noise (we just got a patent for this), and uses
formal technology to verify crossings. Handles multisource FIFOs
and screens false crossings from DFT and power domain isolation."
(booth 633) Ask for Sam Appleton. Freebie: squeezy ninja doll
Real Intent Meridian CDC has "System Verilog and SDC support;
improved bus handling, faster formal engine, new reporting and
configurability that reduces noise; processes 500 M gates of RTL in
12 hours WITHOUT needing abstraction models that SpyGlass and
Questa need." CDC sign-off analysis. Nvidia, Cavium, Magnum.
(booth 1031) Ask Sarath Kirihennedige. Freebie: flashlight
There's a Mentor Questa CDC but I don't know if it's at this DAC.
There was a Cadence Conformal CDC but unsure if it still exists.
FishTail Confirm formally verifies design constraints. Looks like
this year it can check confusing/messy clocks and CDC type stuff
plus weird "case" analysis. "Garbage in, garbage out when it comes
to STA. The source of trash in STA is constraints and STA tools
don't see the trash for what it is." Qualcomm, Xilinx, Altera, TI.
(booth 2325) Ask for Ajay Daga. Freebie: none
Ausdia Timevision also formally verifies design constraints. Does
gate-level and RTL SDC. 20-80M inst, with 1000+ clocks in 8 hours.
Adding fully incremental & SDC promotion/demotion. Full hierarchical
matching tricky block boundary conditions. Maxim, AMCC users.
(booth 633) Ask for Sam Appleton. Freebie: squeezy ninja doll
Excellicon ConMan formaly generates design constraints. Rivals only
do 1 mode/1 hierarchy, ConMan does multi-mode, multi-hierarchy in
one database. SDC promotion/demotion. Auto synth of PrimeTime
case_analysis. (booth 2526) Ask for Himanshu Bhatnagar.
FishTail Focus merges multi-mode PrimeTime STA constraints into one
single super mode. "STARC benchmark 4 M inst netlist with 18 modes.
We merged all 18 modes into a single super-mode. Timing correlation
was within 100 psec pessimism and 10 psec optimism. Cut PrimeTime
runtime 90%." TI, Cypress, Broadcom. (booth 2325) Ask Ajay Daga.
Real Intent Ascent Lint -- Version 2.0 has 60 new rules, new FSM
checks; new Emacs; runs faster and lints 450 M gates 1 hour, with
"no need for hierarchical processing like Atrenta". Nvidia says
they see "50x faster runs vs. Atrenta SpyGlass".
Real Intent Ascent XV does "fast static hazard analysis to find
X-sources and nets susceptible to X-issues. X-optimism bugs are
isolated during RTL simulation. At netlist level, X-pessimism
is identified and corrected. Now does X audits for power-up.
(booth 1031) Ask Lisa Piper. Freebie: flashlight
Avery SimXACT eliminates X bugs in RTL and gate-level simulations
automatically. "New release XOPT SIM to bias RTL simulation away
from X-optimism paths; Safe Deposit Analysis generates list of non-
reset registers at gate-level to deposit safely to at time 0; and
new SimXACT mode for doing focused X pessimism analysis and removal
with sequential backtrace reports of gate-level designs." Broadcom.
(booth 1835) Ask for Chris Browy. Freebie: LED flashlight
Amiq Verissimo SV TB Linter performs code linting for generic System
Verilog code and UVM. (booth 2435) Ask for Cristian Amitroaie.
Synopsys Verdi 3 is the design debug cockpit from SpringSoft
with a Qt-based GUI. Claims to be "open" and supports Verilog,
VHDL, and System Verilog, SVTB, UVM, OVM, VMM, SVA -- but the SNPS
web page won't name specific rival simulators nor rival emulators
nor rival formal tools that Verdi 3 supposedly "supports".(?)
(booth 947) Ask for Thomas Li. Freebie: stylus
Blue Pearl Software Suite speeds FPGA design with RTL analysis, CDC
checks and automatic SDC generation. Gives feedback for validating
automatically generated pre-synthesis longest paths and SDCs.
(booth 1533) Ask for Shakeel Jeeawoody. Freebie: mouse Pad
Cadence IFV doing a "It's the bundled deal, baby!" pitch this year.
(booth 2214) Ask for Joseph Hupcey. Freebie: yawns
Synopsys Magellan competes in formal, but I don't know if it's
showing anything new at this DAC.
POWER & NOISE
8.) JasperGold Low Power App formally verifies lower power designs
that have multiple voltage and power-management domains. Checks
the "correct implementation of the power intent spec, and design
function after the insertion of power management circuitry."
(booth 2346) Ask Lawrence Loh. Freebie: tote bag
NEW! -- Oasys RealTime Power takes entire chip RTL to placed-gates
protype to analyze/estimate/optimize both static and dynamic power.
Does clock gating insertion. Dynamic power analysis supports VCD
stimulus. Power hot spots identified on floorplan view and can be
cross-probed back to RTL block causing the hot spot. Verilog,
System Verilog, VHDL, multi-mode synthesis, DFT, UPF/CPF.
(booth 1231) Ask for Scott Seaton. Freebie: pen
Cadence Conformal LP does equivalency checking "from RTL to xistor
level." (booth 2214) Ask Kenneth Chang. Freebie: Denali tix
Cadence Encounter Power System and Virtuoso Power System does
"power sign-off at gate level (EPS) and transistor level (VPS)."
Competes against Apache RedHawk/Totem, Synopsys PT-PX/PrimeRail.
EPS re-written for massive parallel and hierarchical analysis.
VPS shows unified full custom EMIR solution with APS/XPS/ADE.
Nvidia, TI, Freescale, Broadcom, Fujitsu, Renesas uses both.
(booth 2214) Ask for Jerry Zhao. Freebie: Denali tix
Three RTL power optimizers "because PrimeTime-PX is too late." (i.e.
doing power reductions while at the gate-level doesn't cut it.)
Calypto is mostly known for SystemC/C/C++ SLEC. Yet its PowerPro
users see 9% to 12% power reduction for Verilog RTL. It now supports
UPF and SPEF. "More speed and capacity." AMD, Cisco, HP, TI, Ikanos
use it. (booth 1247) Ask for Thomas Bollaert. Freebies: music CD
Atrenta Spyglass Power users got 9% to 16% power cut on Verilog RTL.
Physical awareness and better accuracy. "More speed and capacity."
Does ECO's, CPF, UPF, mem in sleep mode. Marvell, ST, Broadcom,
Cisco, Juniper, Infinera, Renesas, Infineon, Qualcomm, Samsung users.
(booth 1847) Ask for Guillaume Boillet. Freebie: pen
Apache PowerArtist user saw 3% to 10% reductions. Does automatic and
guided. Sequential and combinational clock-gating constructs, memory
light sleep and deep sleep modes, redundant memory operation, and
wasted power in datapath logic. Ericsson, Nvidia, Renesas, Samsung,
ST, LSI. (booth 1346) Ask for Will Ruby. Freebie: stuffed dog
LibTech ChipTimer does post-synthesis, pre-layout timing, area, power
optimization, and post-layout leakage power opto. Now layout aware.
"First it exhausts the resources of the ASIC lib for ~20-30% better
timing. Creates custom libs 2X better speed. 450 K gate MIPS core
17% faster. Cut 25 K gates, area 2% down, leakage 15% down.
(booth 1443) Ask for Mehmet Cirit. Freebie: none
Docea Aceplorer does power and thermal dynamic simulation and opto at
the architectural level of a chip. Tool is for SoC power architects.
It's for die, I/O, packages, etc. Samsung, Nokia, Huawei users.
(booth 2113) Ask for Philippe Garrault. Freebie: French candy
Ansys/Apache RedHawk DMP does full-chip power integrity analysis and
sign-off, transients, simultaneous switching noise including package
and PCB -- but it now has new distributed machine processing (DMP)
that lets it 500M+ gates, with the accuracy as flat analysis. DMP
did ~2X runtime, ~2.5X less memory vs. flat simulation. Less than
2% accuracy loss, 60M gates and 1.6B design unknowns on 4 machines.
Pathfinder ESD does full-chip multi-domain, multipath electro-static
discharge analysis. Capacity now 2M transistors with critical path
tracing to identify and fix stressed device junctions.
Sentinel-SSO performs full I/O bank timing and noise analysis with
power and signal co-simulation. It analyzes a die-to-die signal path
for entire I/O / DDR bank, plus associated power grid network from
the I/O ring, RDL, package and PCB. Has SPICE-level accuracy.
(booth 1346) Ask for Aveek Sarkar. Freebie: stuffed dog
Invarian Pioneer Analysis are wannabes who compete head on against
Ansys/Apache with a mix of very-longly-named-fragmented-tools that
collectively do power, EM, IR-drop, thermal for chips/package/PCB.
Claims 40 nm and 28 nm "within 2% of real physical measurements."
(booth 1332) Ask for Vladimir Schellbach. Freebie: rulers
Silicon Frontline Ethan does electro-thermal analysis of silicon die
and the package just like Ansys/Apache. Their ESRA does ESD analysis
just like Apache Pathfinder. Work on pre- & post- LVS clean designs.
Does CDM, MM and HBM events. Ask for Yuri Feinberg. Freebie: none
VIRTUOSO & RIVALS
9.) Cadence Virtuoso is the 800 lb gorilla that owns the analog/full
custom layout market. That's why SKILL, PDKs, LEF/DEF are analog
designer terms -- even though they're Virtuoso terms. This year
CDNS is showing LIVE Virtuoso demos on Layout Dependent Effects (LDE)
in 20 nm custom designs. They'll be playing up color-aware 20 nm
custom layout -- something only Virtuoso has. (See ESNUG 510 #1)
They'll also play up Virtuoso "in-design" DRC/LVS with their PVS.
STmicro will be talking on Modgens, too. Ask for John Stabenow.
Virtuoso IPVS does on-the-fly signoff DRC checks as you design. They
will live demo 20 nm DPT realtime color loop detection and 16/14 nm
FinFET special rule checks. ST talks on why IPVS is not an option.
Renesas, Cortina, ST uses IPVS. Ask for Tianhao Zhang.
Virtuoso Digital Implementation (VDI) is for big A, small D designs
to do a analog-on-top or schematic-driven flow. Floorplanning, pin
assignment/optimization, special net routing for mixed-signal blocks.
With VDL-XL, power-gating, MCMM. Specialty tool, no competitors.
(booth 1930) Ask for Mladen Nizic. Freebie: Denali party tix
Analog Rails, the "R.I.P. Virtuoso" start-up, has a full custom
OA-based IC design platform that has schematic, layout, SPICE,
optimization, compactors, nudgers, placers, routers, DRC/LVS, RCx,
EM, IR drop, and differential-aware tilers that "reduces design
time from months to 1 day". Their big thing is AUTOMATED analog
design plus everything is synchronized -- all the parts (schematic,
layout, SPICE, DRC, etc.) all constantly share the same info.
(booth 1240) Ask for Cliff Wiener. Freebie: stolen CDNS pens
Synopsys Laker Custom Designer marries their 6 years of SNPS R&D on
top of the $305 M SpringSoft acquisition. This DAC will show how in
a Frankenstein fashion parts of Custom Designer and Laker were welded
together -- thus keeping R&D in both companies happy (and employed!)
(booth 947) Ask for Paul Lo. Freebie: stylus
Mentor PyxisOpen is a fully rewritten constraint-driven hybrid grid
and shape-based full custom router that runs native on OpenAccess.
Hierarchical cells without abstracts, propagates signal constraints
up through the hierarchy to ensure clean routing at all levels.
"We're baaack!" (booth 2046) Ask Tom Daspit. Freebie: stuffed bat
ClioSoft Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Now hierarchical.
Work with DesignSync & IC Manage. Marvell, Toshiba, TSMC, ADI users.
NEW! -- ClioSoft SOS viaPyxis does design data management with
Mentor OpenPyxis. Enterprise-wide rev control, design management
and multi-site team collaboration support for the new OpenPyxis.
(booth 2125) Ask for Karim Khalfan. Freebie: racing cap
Tanner EDA sells OA-based S-Edit schematic capture, L-Edit custom
layout, HiPer Verify DRC, and T-Spice SPICE. Founded 1988. Known
for their "cost effective" pricing. Not bad for the cheap seats.
(booth 2442) Ask for John Zuk. Freebie: safety whistle
VERIFICATION IP
10.) Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
- have VIP for "AMBA4 ACE, DDR4, eMMC 4.5, Ethernet 40/100G,
LPDDR3, LRDIMM, MIPI LLI, MIPI CSI-3, NVM Express, ONFi 3.0,
SATA 6G, SD Card 4, SSIC, UFS, Wide I/O."
- added a Denali-style API, all simulated VIP now runs on VCS,
Questa and Incisive. "VCS or Questa customers do not need
Specman, as support for the e language is built into our
simulator interface."
- TripleCheck, their IP validation tool is in its 3rd rev.
- "We have assertion-based VIP for the AMBA protocols and OCP."
Works with Cadence IFV.
This year they're chatting up their Accelerated VIP (AVIP); comes in
super fast flavors now. Apple, ARM, Broadcom, HP, IBM, Intel, LSI,
Hitachi, Marvell, Qualcomm, Samsung, AMD, ST all use Cadence VIP.
(booth 2214) Ask Frank Schirrmeister. Freebie: Denali party tix
Synopsys Discovery Verification IP (VIP) is "100% System Verilog with
native UVM, OVM, VMM support" and "superior ease-of-use" because
Cadence VIP uses "wrapping layers that significantly hamper" run
times. Also showing Synopsys Protocol Analyzer, "simulator-neutral
debug environ" for protocols like USB, PCI Express, AMBA, OCP, etc.
(booth 947) Ask for Neill Mullinger. Freebie: stylus
Avery Xactor now has in VIPs for SSDs and embedded flash memory, NVM
Express, SCSI Express (SOP/PQI), SATA Express, UFS, eMMC, SD/SDIO, and
UASP, DDR/LPDDR memory models. Seagate, Samsung, Broadcom use them.
(booth 1835) Ask for Chris Browy. Freebie: 4-in-1 flashlight
CALIBRE & RIVALS
11.) Calibre nmDRC and Calibre Multi-Patterning now has 6X speed-up, 2X
cut in CPU time, and a 4X memory reduction. It does it all: CMOS,
NMOS, PMOS, BiCMOS, FD-SOI, FinFET 20 nm (N20 and 20LPM) and 16/14 nm
(N16, 14LPE, 14XM). Supports more complex equation-based DRC checks,
voltage-based DRC checks and double patterning checks. 10 B devices
and full reticle sized designs now done 16 hours overnight. Calibre
is the golden sign-off for TSMC, Samsung, GlobalFoundries, UMC.
Calibre RealTime lets engineers do instantaneous sign-off DRC during
layout creation. "Same deck, same results as batch Calibre." Does
double patterning, pattern matching, voltage-aware DRC, and density
checks -- just like "batch" Calibre. Claims "2X productivity" at
20/16/14 nm. Winner of the 2012 Elektra Design Tool Award.
SAY AGAIN??? -- Calibre PERC will have SMIC do a talk about PERC for
reliability checking, ESD, latch-up, EOS, ERC and stream out DBs;
but in Mandarin Chinese! (Sawicki knows Austin's in Texas, yes???)
Later, for English speakers, TowerJazz will talk about DRC/LVS of
legacy processes in Calibre PERC. ESD, and automated checking.
Mentor Calibre will have TSMC taking on 20 nm "best practices" that
improved 20 nm signoff runtimes by 3X and memory cuts by 60% compared
to last year -- 20 nm runs pushing reticle sizes done in 16 hours.
Samsung, Freescale, IBM, ST, Infineon, TSMC, MStar, SMIC, GF, UMC.
(booth 2046) Ask Dave Abercrombie or John Ferguson. Freebie: bat
Cadence PVS is the great great grandchild of the olde Dracula DRC/LVS
that at one time had 95% marketshare. Looking for a comeback, CDNS
it does 20 nm double patterning, 3D-IC, device extraction, plus
reliability checking and constraint validation. Like Calibre and
ICV, PVS does similar "in-design" with CDNS Encounter and Virtuoso.
On Friday, PMC announced it used PVS for 65/40/28 nm DRC sign-off.
(booth 1930) Ask for Tianhao Zhang. Freebie: Denali party tix
Aart bailed on Hercules at 45 nm, and has since been focused on
selling his Synopsys IC Validator for DRC/LVS. It's tightly coupled
with his IC Compiler; many say ICV got a boost when Magma Quartz DRC
was added. IC Validator's locked with ICC; it's not as a standalone
DRC/LVS tool. (booth 947) Ask for Mark Bollar. Freebie: stylus
NEW! -- Sage iDRM is a physical design rule compiler. Like the
"in-design" aspect of Calibre in Olympus or ICV in ICC, you enter
your design rule into its GUI and it finds all the places in your
physical design where that rules applies -- plus where it's been
violated. It helps make sensible DRC decks. Lattice uses iDRM.
(booth 2233) Ask for Coby Zelnik. Freebie: a free demo
Coventor SEMulator3D is a tool for the fabs themselves to simulate
the manufacturing process. Virtual fabrication. Model etching of
multi-material stacks with redeposition (passivation), sputtering
(physical etching), and etch bias (lateral or chemical etching).
(booth 1326) Ask for David Fried. Freebie: none
MARGINs & ECOs
12.) CLK-DA Margin evaluates all cells (combinatorial and sequential),
all arcs, all loads, all slews for process, temp, voltage, and
constraints - 1 hour per PVT corner for 1000 cells on 200 uP's
to create a 'variance database' to build AOCV tables, POCV tables,
or perform cell or lib sensitivity analysis. Claims to have "big
name" users -- but so far not one has stepped up to review them.
(booth 1015) Ask for Isadore Katz. Freebie: mints
Dorado Tweaker is a family of physically-aware ECO tools:
Funct. ECO / Timing ECO / Power ECO / Metal ECO / Clock ECO
Tweaker-F1 / Tweaker-T1 / Tweaker-P1 / Tweaker-M1 / Tweaker-C1
Synopsys PrimeTime-ECO vs. Tweaker-T1
Cadence Conformal-ECO vs. Tweaker-F1
ICC, SOC Encounter, AtopTech, old Magma. Incremental and partial.
Tweaker-T1 runs 5.5 hours to clean 97% of (400 K+) hold violations
1.55 M inst block with 72 scenarios with only 1 license and 1 CPU.
Their 2nd DAC. So far no one has confirmed how well/poorly these
tools do. (booth 1718) Ask for JJ Hsiao. Freebie: magic ball
ICScape TimingExplorer is a physically-aware MCMM timing ECO tool.
"ECOs done 50% faster, reduce clock latency 50%, cut leakage 40%."
This year added metal-only timing ECO and transition fix by rerouting.
(booth 1519) Ask Ravi Ravikumar or Jason Xing. Freebie: baseball cap
Cadence Conformal ECO Designer this year tersely claims it does
"ECOs on hierarchical designs". Ok... Users: Cisco, ST, Fujitsu.
(booth 2214) Ask Kenneth Chang. Freebie: Denali party tix
IP TOOLS
13.) IC Manage IP Central maximizes your internal IP reuse -- can be
a mix of homebrew and purchased IP. Trace bug dependencies. Fixes
across all IP versions and designs. Bug history viewable. Was a
DAC'12 #2 pick. Broadcom, Altera, Nordic Semi, Samsung uses it.
New this year is "checklist driven design" and testbench reuse.
(booth 1041) Ask for Shiv Sikand. Freebie: chocolates
Atrenta SpyGlass IP Kit checks soft IP for problems, plus definitions
of the rules to run, scripts to automate the process, documentation,
and a test design to make sure everything is installed correctly.
Does routing congestion analysis and Cyclomatic complexity scores;
a measure of the number of paths through a piece of code. It's
"competitors" are ChipEstimate.com and the GSA IP Quality Metric.
What's big is how many companies use the SpyGlass IP Kit: TSMC, ST,
TI, Renesas Mobile, ARM, Ceva, Sonics, Arteris, DMP, Imagination,
Intrinsic-ID, Tensilica, Vivante, Authentec, Discretix, MIPS, PLDA,
Cosmic Circuits, GUC, Evatronix, Dolphin, IPextreme. IPextreme
will demo IP Kit running in their cloud-based Xena environment.
Atrenta GenSys Assembly does IP integration, chip assembly, automated
RTL generation. Competes vs. Synopsys CoreAssembler or Duolog Weaver
of Magillem Platform Assembly. Claims 20-30X faster than IP-XACT.
Live hookup error checking. Generates RTL netlist. Does hierarchy
manipulation, group/ungroup IP, IP movement while preserving existing
connectivity. SDC validation. Physical congestion and timing.
TI, Sandisk, Broadcom, ST Microelectronics, LG, Canon, Renesas.
(booth 1847) Ask for Kiran Vittal. Freebie: pen
FABS
14.) After few pesky yield/capacity troubles, TSMC can proudly claim it
easily owns 28 nm. The big tech battle then was gate-first vs.
gate-last -- and Hsinchu chose the winning side. Now the fight has
moved to 20 nm -- with the big tech question being TSMC FinFET vs.
GlobalFoundries FD-SOI. (booth 1746) Ask for Suk Lee.
And at this DAC you'll see a more wiser GlobalFoundries this time
chatting up BOTH their FinFET and FD-SOI offerings -- but don't be
fooled -- they'd REALLY like it if you went FD-SOI because to their
big investment in it. (booth 1314) Ask for Mike Noonan.
Oh, and that company, Samsung, that made $1 billion worth of chips
for Apple last year? They're in (booth 915). Ask for Pierre Golde.
Intel 14 nm is the one thing that strikes true terror in the hearts
of all the other fabs -- their fear is they'll be at the one trade
show where Intel finally shows it off -- and steals their customers.
(booth 531) Ask for ??? Freebie: empty TSMC/GF/Samsung booths
TowerJazz does iPDK's for its volume 130 nm digital & AMS customers.
(booth 1736) Ask for David Postula or Russell Ellwanger.
MOSIS combines many companies' designs into one wafer run for low
volume and prototyping production. GF, IBM, TSMC. (booth 1441)
CMP does prototyping and low volume IC production. CMOS, SiGe,
BiCMOS from ST. CEA-LETI 20 nm FDSOI. GloFlo 3D-IC. (booth 2242)
WORKSPACE & DESIGN DATA MANAGMENT
15.) IC Manage Views and Zero-Time Sync lets engineers get their EDA
tools populated on their desktop very quickly. Claims "1 gigabyte,
10,000 file work-space in 1 second to populate." Broadcom benchmark
saw 2 GB in 15 sec. Allows memory-piggy EDA tools to run immediately!
2x faster file access and speeds up applications through "automated
intelligent file redirection". This year you no longer wait to sync.
IC Manage GDP does data management for digital and custom designers to
find, modify, release and track design data through to tapeout. Now
more bug dependency management stuff this year. Samsung, Altera, AMD,
Maxim, Nvidia, Broadcom, Nordic Semi, CSR, GlobalFoundries users.
(booth 1041) Ask for Shiv Sikand. Freebie: chocolates
ClioSoft SOS does HW configuration management & rev control for full
custom Virtuoso, Laker, Pyxis, and Synopsys Custom Designer. Built-in
IP management and reuse. Does soft integrations with in-house flows.
SOS 7.0 Beta is re-architected to be super-fast and highly scalable,
ADI, Dongbu, Huawei, Lattice, Oracle, Marvell, Toshiba, TSMC users.
(booth 2125) Ask for Karim Khalfan. Freebie: racing cap
Runtime FlowTracer automates your design flow across 1000's machines.
Compute farm record 1.5 M jobs, 18 M files in 1 single customer flow.
License and network montoring products, too. Competes vs. LSF/GRID.
(booth 2042) Ask for Andrea Casotto. Freebie: none
SystemC/C/C++ STUFF
16.) After a decade of watching Forte and Mentor/Calypto endlessly bicker
over which of them was #1 in the SystemC-to-Verilog RTL synthesis
marketshare numbers, and then seeing Cadence's Phil Bishop blurt out
in ESNUG 521 #4 that Cadence C-to-Silicon Compiler has "31 customers
on 58 active production projects" -- for C stuff this year I'm going
to the CDNS booth to see what I've been missing.
C-to-Silicon takes in untimed SystemC and generates Verilog RTL that
Design Compiler and RTL Compiler can easily digest. "2x turnaround
in verification vs. an RTL approach" and "IP re-use is much simpler
when all you have to do is change constraints, not re-code your
micro-architecture. Casio, Freescale, Fujitsu, Ikegami, Sunplus.
(booth 2214) Ask for Phil Bishop. Freebie: Denali party tix
Calypto Catapult synthesizes SystemC/C/C++ to Verilog RTL. "First
to deliver C assertion and coverage-driven verification." Toshiba,
STMicroelectronics, Fujitsu, Fuji Xerox, ST/Ericsson, Fraunhofer.
(booth 1226) Ask for Thomas Bollaert. Freebie: Calypto music CD
Forte Cynthesizer synthesizes SystemC to Verilog RTL. Ver 5 now goes
low power. "Just released a SystemC IDE making it faster to create
and debug SystemC designs" and "joint session on low power design with
Ansys-Apache". Samsung, LG, Sony, Realtek, Toshiba, Ricoh, Fujitsu.
(booth 1547) Ask for Brett Cline. Freebie: beer
NEC CyberWorkBench does C/SystemC into Xilinx/Altera FPGAs. Has low
power and auto architecture exploration. Both control intensive and
data dominant designs. Debugging can be done early in C/SystemC.
Mitsubishi, Advantest, Panasonic, Fujitsu, Hitachi, Toshiba, Renesas.
(booth 2225) Ask for Kazutoshi Wakabayashi. Freebie: trick game
Synopsys Synphony C Compiler, the old Synfora stuff, also does some
C synth but I'm unsure if they will be showing it at this DAC.
Cadence Virtual System Platform lets you write and debug SystemC
models that run screaming fast -- even faster on Palladium and RPP.
Competes vs Synopsys Virtualizer, Mentor Vista, Carbon SoC Designer.
(booth 2214) Ask Frank Schirrmeister. Freebie: Denali party tix
Calypto SLEC does SystemC/C++/C-to-RTL functional equivalence. Tight
with Catapult; less tight with Forte or C-to-Silicon. It now does
assertion and property checking for C++. Rivals CDNS Conformal.
(booth 1226) Ask for Thomas Bollaert. Freebie: Calypto music CD
Carbon Performance Analysis Kits are pre-built virtual prototypes and
software for ARM Cortex-A9, Cortex-A15, Cortex-A7 and this year they
added a "100% accurate model of the ARM Cortex-A57" and "also has
CCI-400, DMC-400, GIC-400, NIC-301, etc." Competes vs. emulators.
(booth 921) Ask for Bill Neifert. Freebie: none
Breker TrekSoC generates multi-threaded, multi-processor, multi-mem
C test cases to verify embedded SoCs from inside out. Broadcom, ST.
(booth 2015) Ask for Tom Anderson. Freebie: none
Vayavya DDGen generates device drivers in ANSI-C from high level spec
device & software specifications - for Linux or other OSs. IP-XACT.
(booth 1929) Ask for Sandeep Pendarkhar. Freebie: USB flash drives
Target MP Designer automates the parallelization of ANSI C code across
multiple distinct/different processors. (booth 2142) Ask Steve Cox.
TEST/SCAN/BIST/JTAG
17.) Mentor Tessent IJTAG automates the IEEE P1687 IJTAG standard, by
making test itself a reusable IP block -- clever idea. Although
Wally has some brilliant test brainiacs, they tend to only want to
hang out at ITC with other test brainiacs. If you find one at DAC
ask him/her/it to explain IJTAG. I'm serious; it's really neat!
(booth 2046) Ask for Steve Pateras. Freebie: stuffed bat
NEW! -- DeFacTo Signoff ATPG has some really curious test stuff where
it can do ATPG on your Verilog RTL *before* you do any synthesis. I'm
not exactly sure how it works. (booth 409) Ask for Chouki Aktouf.
Atrenta SpyGlass DFT does "RTL analysis for stuck-at/at-speed
testablity, low power design, JTAG/IEEE1500" and "RTL fault coverage
estimation for stuck-at, transition and random-resistive faults."
It competes against DeFacTo. Finds "hard-to-test" or "random
resistive" faults. Qualcomm, TI, ST, Mediatek, Canon, Cisco users.
(booth 1847) Ask Kiran Vittal. Freebie: pen
HARD & SOFT IP
18.) Cadence Design Systems' new comeback tactic against Synopsys is to
go on a massive buying spree of IP companies. In the past 12 months
they've acquired TenSilica, Cosmic Circuits, Evatronix... One of the
first people I'd ask about this would be Martin Lund on what's next?
(booth 2214) Ask Martin Lund. Freebie: CDNS' IP strategy explained
And again on the DAC floor this year ARM Ltd. is in a gaudy monster
big $$$ marketing blitz to drive home that 950 companies "from
design to manufacture and end use" are in bed with big momma ARM.
It's A-to-Z in the 16 dwarves orgy -- Apache, Ateris, Carbon,
Sonics, SpaceStudio, Tanner, Zolcalo -- plus the Big 3: Synopsys,
Mentor, Cadence all taking turns in the money shots. (booth 921)
On the technical, non-marketing-blitz side, ARM, Inc. is showing its
same old 32-bit RISC CPU, mem IP, and std cell libs. (booth 931)
Synopsys sells Virage DW ARC 600 & 700 family of cores, plus Virage
mem IP, plus Virage InChip std cell libs that all directly compete
against ARM. 170 customers. This year DW ARC comes in low power
and audio flavors. Also "extensive SystemC support and Synopsys
Virtualizer and PA-MCO virtual prototypers" plus "ARC starter kit".
ARC for Android and Linux! Ask for Mike Thompson. (booth 947)
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precision clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 1841) Ask for Mahesh Tirupattur. Freebie: none
Cambridge Analog Tech sells ultra-low power ADCs, DACs, PLLs, TDCs,
analog front ends. (booth 719) Ask for Kush Gulati.
Cortus SA sells ultra low power 32-bit microcontoller IP cores; four
types: RISC to floating point. (booth 1924) Ask Michael Chapman.
Ensilica Ltd. sells configurable 16/32-bit eSi-RISC, eSi-Crypto,
eSi-Comms, eSi-Connect. (booth 1336) Ask for Ian Lankshear.
PLDA sells IP for SuperSpeed USB, PCI Express, PCI-X, 10Gb TCPIP
for ASICs and FPGAs. (booth 1524) Ask for Jean-Yves Brena.
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". (booth 2245) Ask for Micke Wersall.
Tela Innovations sells libs for "restricted design rules", double
patterns, FinFET 32/14 nm. (booth 1815) Ask for Scott Becker.
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180 nm to 28 nm. (booth 2441) As for John Maneatis.
Uniquify sells DDR Memory Controller subsystem IP. Has dynamic
self-calibrating logic. (booth 1941) Ask for Mahesh Gopalan.
Forte CellMath Floating Point IP competes vs. Synopsys Designware on
high-level math functions like: IEEE rounded functions: add, mul, div,
and sqrt; Non-IEEE rounded functions: add, mul, dot-product; Single
input combinational functions: recip, recip-sqrt, log, exp, sin, cos,
and sqrt. Wide range of precision, rounding modes, and bitwidths.
(booth 1547) Ask for Nick Atkinson. Freebie: beer
Codasip Framework is ASIP (application processor) development environ
that generates a C/C++ compiler, debugger, synthesizable RTL and UVM
based verification. HUH??? (booth 2333) Ask Karel Masarik.
Target IP Designer automates the development and verification of
specialized processors (aka ASIPs), including SDKs that allow people
to program them using ANSI C. (booth 2142) Ask Steve Cox.
SEE YOU AT DAC
19.) If you're at DAC and you want to hook up to talk trash, on DAC Sunday
I'll be at Gary Smith's pre-DAC talk at:
Sunday 5:00-5:30 pm, Ballroom ABC, Austin Convention Center
and on DAC Monday, I'll be moderating my DAC Troublemakers Panel at:
Monday, 3:00-4:00 pm, Ballroom G, Austin Convention Center
Word is Wally Rhines, Lip-bu Tan, Kathryn Kranen, JL Grey, Gary Smith,
Joe Costello, Suk Lee, Richard Goering, Raul Camposano, Dean Drako
all donated to charity to be at Jim Hogan's Hot Zone VIP party at
8:00 to 1:00 on DAC Monday at Austin City Limits. See you there!
Anyway, I'll see you at DAC! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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