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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2014"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
You might want to print out a hardcopy of this as an unofficial guide to the
San Francisco DAC'14 exhibit floor. List ranked in order of importance.
DIGITAL P&R
1.) Cadence Encounter EDI "Project Novus" is easily the first thing I'll
want to check out at this DAC. Why? News of "Project Novus" just
broke last week in ESNUG 541 #5 -- it's what Anirudh was privately
telling CDNS customers on how he planned to defeat Aart's ICC II.
Project Novus EDI has a new unannounced placer called GigaPlace.
A unified GUI for STA/P&R/synth. MCMM speed-ups. And NanoRoute
now does faster global routes. Massive parallelism. One customer
took 39 min to route a 28 nm 4.6 M cell design. A 9x speedup of
4-CPU vs. 64-CPU runs. ARM-specific optimizations rumored, too.
Officially Cadence Encounter EDI this year now "prototypes 100 M+
instance chips in 1 day with FlexModels. New GigaOpt power-driven
optimizations for 50% less leakage. CCopt is natively integrated,
1.5X faster and provides 10% better PPA." EDI users are: Samsung,
STMicroelectronics, TI, Fujitsu, Spreadtrum, Marvell, and Renesas.
(booth 2616) Ask for Kam Kittrell. Freebie: Denali party tix
Atoptech Aprisa gets my interest next because Aart's lawyers are
suing them -- so ATOP must be doing something right. ATOP now has
16/14 nm fab certifications, 2X runtime, 15-20% dynamic power
reduction. Their Apogee floorplanner prototypes RTL partitions
hierarchically as flat physical. Broadcom, Samsung, PMC Sierra.
(booth 1023) Ask for Daniel Maung. Freebie: flying pigs
Mentor Olympus-SoC is showing off its new Oasys RealTime Designer.
It's now a complete RTL-to-GDSII flow! Now does RTL estimation,
Verilog/VHDL synthesis, floorplanning, design partitioning and
pre-CTS optimization -- *before* MCMM P&R. Olympus-SoC itself now
does full-chip RTL-to-physical synthesis, "Place First", and design
space PPA exploration. Also does multi-patterning, FinFET aware,
extraction, and DRC/MP signoff. ST, Hitachi, Nvidia are users.
(booth 1733) Ask for Sudhakar Jilla. Freebie: Lego kit
Synopsys will be simultaneously showing IC Compiler, which is
commonly used, and IC Compiler II, with only 7 design starts.
Expect no news at DAC they didn't already say before at SNUG'14.
(booth 1133) Ask for Saleem Haider. Freebie: pens
SPICE & AMS
2.) MENT BDA Analog FastSPICE (AFS) is 5x-10x faster vs CDNS Spectre in
ESNUG 495 #4 and 2x faster than SNPS FineSim Pro in ESNUG 535 #3.
10+ M elements. TSMC 16 nm certified. BDA ACE fully replaces
Virtuoso ADE-XL for analog characterization runs. AFS Mega does
SPICE of 100+ M element mega arrays like memories. It does DC,
transient, transient w/ dynamic temp, alters, sweeps, Monte Carlo.
TSMC uses AFS Mega for 16 nm. Over 100 companies use BDA tools.
(booth 1119) Ask for Scott Guyton. Freebie: Lego kit
CDNS Spectre-XPS is Lip-bu's comeback Fast SPICE tool. Has all the
new bells & whistles for fast, accurate simulation of large, memory-
intensive and mixed-signal designs. Has clever fast-or-accurate
proprietary partitioning based on need. Multi-core simulation.
(booth 2616) Ask for John Pierce. Freebie: Denali party tickets
ProPlus NanoSpice Giga big ass capacity parallel SPICE. Did 576 M
element full-chip DRAM, 50.5 M transistor SRAM and 67 M element post-
layout SRAM. "10x+ speedup over other parallel SPICE on long runs."
(booth 905) Ask for Lianfeng Yang. Freebie: cell phone clip
EDXACT Jivaro does SPICE acceleration by netlist reduction. Reduces
netlist resistors with temperature coefficients, negative resistors,
some active devices. Mediatek, TSMC, Huawei, Toshiba, Faraday users.
(booth 527) Ask for Mathias Silvant. Freebie: pens
Solido Variation Designer does variation-aware custom IC design for
PVT corner analysis, 3-7 sigma Monte Carlo and variation debug. Big
thing is it cuts waaaaaaaaay down on how many SPICE runs you need.
Does 20 M devices, 3.2 G netlists capacity, new GUI and CLI, 20x
faster high-sigma Monte Carlo for large designs, FinFET support.
Users Broadcom, TSMC, Avago, Nvidia, Huawei, Sidense, NSCore, Inphi.
(booth 933) Ask for Amit Gupta. Freebie: none
MunEDA WiCkeD High-Sigma analyzes SRAM cell/column/array, std cell,
analog circuits for local variation to 9-sigma. Yup. 9-sigma!
Samsung, SK Hynix, ST Micro, Sanyo, Toshiba, and Altera users.
(booth 2213) Ask for Andreas Ripp. Freebie: tote bags
ProPlus NanoYield is variation analysis on yield vs. PPA trade-off.
It does High Sigma Monte Carlo. Licensed from IBM six years ago.
Can handle 10,000+ variables and does up to 7-sigma. Used by SMIC.
(booth 905) Ask for Lianfeng Yang. Freebie: cell phone clip
Infiniscale IClys does Monte Carlo to 50X, and High-Sigma analysis
1000,000X and variability analysis of well proximity effects.
(booth 427) Ask for Firas Mohamed. Freebie: pens
Cadence Virtuoso Liberate LV/MX/Variety is new name of Altos cell lib
characterizer. Does electrical cell views for timing (NLDM), power
(NLPM) and signal integrity. CCS, ECSM, CCSN, ECSMN, AOCV/SOCV/LVF.
Likes Spectre. Rivals are Liberty NCX, SiliconSmart, Mentor Kronos.
(booth 2616) Ask for Ahmed Elzeftawi. Freebie: Denali party tix
Integrand EMX is a 3D EM simulator for modeling on-chip passives
and interconnect and RF. Now black boxing models active circuitry.
Samsung, Broadcom, Nvida, MediaTek, TSMC, GloFlo, UMC, IBM, Fujitsu.
(booth 1000) Ask for Sharad Kapur. Freebie: stress doll
Helic VeloceRaptor/X does rapid, high capacity, electro-magnetic
inductance aware modeling of on-chip interconnect and passives.
(booth 2323) Ask for Anand Raman. Freebie: squeeze baseball
Cadence QRC Extraction competes with Star-RCXT and Calibre-XRC.
Does multi-corner/statistical/inductance RLCK extraction, 16/14 nm
modeling, distributed processing, netlist reduction, SNA. Yeehaw!
(booth 2616) Ask for Hitendra Divecha. Freebie: Denali party tix
IROC Tech TFIT predicts soft error FIT rate on CMOS digital cells.
(booth 817) Ask for Olivier Lauzeral. Freebie: none
EMULATION / ACCELERATION / PROTOTYPING
3.) Cadence Palladium XP II has functional coverage, dynamic power
analysis UPF/CPF, full ICE 10x speed-up into Mhz range without loss
of analysis data. New use models for embedded test benches and
hybrids with virtual platforms, for system environment virtualization
and 60x faster software bring-up. 2.3 billion ASIC gates. 512
simultaneous users. 2X faster. TI, Broadcom, AMD, Nvidia, CSR,
Freescale, Samsung, LeCroy, Sharp, PMC use Palladium XP II boxes.
Their CDNS ARM System Development Suite is optimized for ARM v7 and
v8 based chips, HW/SW co-design, debug, interconnects, OS bring-up.
(booth 2616) Ask Frank Schirrmeister. Freebie: Denali party tix
MENT Veloce 2 now does 50 MHz embedded SW execution with their new
Warpcore, and 50 MHz SW debug with Codelink. VirtuaLAB peripherals:
256-port Ethernet, PCIe Gen3, USB-3, Multimedia, SATA, SAS, VJTAG.
New Visualizer RTL-waveform debugger. UPF low power, assertions,
System Verilog functional coverage. Claims fast bring-up, too.
Broadcom, Mitsubishi, NXP, ST, Trident, ZTE, HiSilicon uses it.
(booth 1733) Ask for Jim Kenney. Freebie: Lego kit
Synopsys EVE ZeBu-3 claims to be 4X faster and do 3 B gates. TLMs,
power-aware, simulation acceleration, ICE, synthesizable testbench.
Claims small footprint, low weight, and very modest power/cooling.
(booth 1133) Ask for Tom Borgstrom. Freebie: pen
Cadence Rapid Prototyping Platform is an FPGA-based prototyper to
model your ASIC in FPGAs. Lip-bu's answer to SNPS HAPS. Automatic
ASIC-to-FPGA memory conversion, clock tree transformation, and
pre-P&R model validation. "quick bring up is in 4-6 weeks instead
of 3-4 months." Freescale, Nvidia, Hitachi, ARM uses RPP.
(booth 2616) Ask for Juergen Jaeger. Freebie: Denali party tix
Synopsys HAPS-70 S48 and ProtoCompiler claims 288 M ASIC gates,
2X faster, automated partitioning. 24 Xilinx Virtex-7 2000T's.
(booth 1133) Ask for Mick Posner. Freebie: pens
S2C TAI Logic Module is like SNPS HAPS, FPGA-based rapid prototyping
of chips. Uses Mentor Vista and Mentor CodeBench Virtual Edition.
(booth 533) Ask for Toshio Nakama. Freebie: pens
ProDesign proFPGA is like SNPS HAPS but based in Germany. Mix match
Xilinx Virtex 7 330T to 2000T to Altera Arria 10. 240 M ASIC gates.
(booth 2405) Ask for Martin Langner. Freebie: hugs
Aldec HES-7 claims 96 M gates. Auto partitioning, ASIC-to-FPGA
clock conversion, static/dynamic probes, memory viewer, triggering,
HW breakpoints. Interfaces: Ethernet, USB, USB-OTG, HDMI, I2C, SPI,
RS232, GPIO, ARM Debug & JTAG. Fuji-Xerox, Sandia, Textron users.
Their HES-DVM does System Verilog DPI-C TLM's, virtual SW, ICE.
(booth 1521) Ask Piotr Bajorowicz. Freebie: clock
Flexras Wasga Compiler does timing driven partitioning for FPGA-based
rapid prototyping of ASICs. Virtex-7. Wasga Architect input HDL
design, interfaces, speed. Output a custom FPGA-based board netlist.
(booth 304) Ask for Matthieu Tuna. Freebie: none
Dini Group TOE/TOE128 is a TCP IP offload engine for high frequency
stock trading. You know, as in shares of GOOG at $565.95 is +2.4%?
Millennium IT uses it for the London Stock Exchange and Barclay.
(booth 2401) Ask for Mike Dini. Freebie: ???
POWER/NOISE/THERMAL
4.) NEW! -- Cadence Voltus is Lip-bu's attack on Apache/Ansys RedHawk.
It does does full-chip power integrity analysis/signoff, IR-drop,
Power-Grid-View models. Massively parallel. 1B instances. Works
with CDNS Tempus and Sigrity chip/package/board. Early user cut
runtime from 9 days to 1 day on a large ARM design. Also customer
benchmark in ESNUG 541 #1. Nvidia, Cavium, Toshiba, Fujitsu, TI.
(booth 2616) Ask for Jerry Zhao. Freebie: Denali party tickets
Ansys/Apache RedHawk DMP does full-chip power integrity analysis and
sign-off, transients, simultaneous switching noise including package
and PCB with distributed processing. 3X less memory footprint,
100 M instances, 2 B nodes maintaining flat simulation accuracy.
Vector-based and vectorless. Clock jitter. TSMC 16 nm FinFET.
Their Pathfinder ESD does full-chip multi-domain, multipath electro-
static discharge analysis. Capacity 2M transistors with critical
path tracing to identify and fix stressed device junctions. Their
Sentinel-SSO performs full I/O bank timing and noise analysis with
power and signal co-simulation. It analyzes a die-to-die signal path
for entire I/O / DDR bank, plus associated power grid network from
the I/O ring, RDL, package and PCB. Has SPICE-level accuracy.
(booth 1413) Ask for Ravi Ravikumar. Freebie: stuffed dog
Invarian Pioneer Analysis competes head on against Ansys/Apache
doing power, EM/IR and thermal "all with confirmed 1-2% accuracy".
Fully TSMC 20/16 nm FinFET certified. ESD tool 10x runtime.
(booth 706) Ask for Vladimir Schellbach. Freebie: rulers
NEW! -- MunEDA Low Power optimizes analog/RF/custom digital circuits
for low power. FinFET / FD-SOI, capacity 2000 MOS, 200 variables,
support for Agilent Goldengate and Empyrean Aeolus, constraints
for aging & reliability. Samsung, ST, Altera, Faraday, Infineon.
(booth 2213) Ask for Michael Siu. Freebie: mouse pads
Silicon Frontline ESRA does ESD analysis just like Apache Pathfinder.
Shows ESD events that cause non-ESD device failure. Their P2P-RMAP
finds power-net high resistance spots, soft connects, disconnects.
(booth 1719) Ask for Yuri Feinberg. Freebie: none
Magwel NV ESDi also does ESD analysis just like Apache Pathfinder.
It can now handle chips as big as 10x10 mm^2 with up to 1000 pins.
(booth 1601) Ask for Olivier Dupuis. Freebie: none
Entasys PadOptima optimizes the number and location of power pads to
meet your target IR-drop and SSO noise margin. Samsung, LG users.
(booth 1501) Ask for JJ Park. Freebie: pens
Calypto PowerPro does RTL power optimization. Users see 9% to 12%
Verilog RTL power savings. UPF and SPEF. Only tool tight with
their SLEC-Pro sequential equivalency checker that verifies their
low power RTL tweaks are functionally equivalent to original RTL.
New physically-aware: models clock tree, multi-Vth libraries, SPEF
extraction of WLM. Has seen 85% correlation against gate-level.
(booth 2333) Ask for Anand Iyer. Freebie: USB charger
Atrenta Spyglass Power users got 9% to 16% power cut on Verilog RTL.
Physical awareness and better accuracy. Does ECO's, CPF, UPF,
mem in sleep mode. Now does ERC checks on P/G netlist. Support
of UPF 2.1. Also now does power modeling and coarse clock gating.
Broadcom, Cisco, Juniper, Infinera, Infineon, Qualcomm, Samsung.
(booth 1933) Ask for Guillaume Boillet. Freebie: USB charger
Apache PowerArtist user saw 3% to 10% reductions. Does automatic and
guided. Sequential and combinational clock-gating constructs, memory
light sleep and deep sleep modes, redundant memory operation, and
wasted power in datapath logic. Now does 100 M instances and clock
power modeling at RTL. Nvidia, Renesas, Samsung, ST, LSI, Ciena.
(booth 1413) Ask for Preeti Gupta. Freebie: stuffed dog
JasperGold Low Power App formally verifies lower power designs
that have multiple voltage and power-management domains. Checks
the "correct implementation of the power intent spec, and design
function after the insertion of power management circuitry."
(booth 2033) Ask Lawrence Loh. Freebie: tote bag
NEW! -- Avery RetentSYN analyzes power transition and functional
simulation sequences in RTL and gate-level designs to auto minimize
the use of retention registers to reduce area and leakage power.
Makes optimized UPF retention register commands. Broadcom uses it.
(booth 1225) Ask for Chris Browy. Feebie: flashlight
LibTech ChipTimer does post-synthesis, pre-layout timing, area, power
optimization, and post-layout leakage power opto. Layout aware.
"User ARM std cell core at 20 nm, area cut 20% and timing cut 15%."
(booth 1326) Ask for Mehmet Cirit. Freebie: none
NEW! -- Docea ThermalProfiler does fast simulation at chip and
board level of dynamic thermal power. Thermal/leakage coupling.
Made for a customer who had a bad thermal runaway surprise.
(booth 2113) Ask for Philippe Garrault. Freebie: French candy
Ansys Sentinel-TI does thermal reliability checks for FinFET-based
designs. Models self-heating. Thermal-aware EM methodology.
Handles 30 chips in one 3D-IC package. Tile-based heat sources.
(booth 1413) Ask for Norman Chen. Freebie: stuffed dog
Cadence Sigrity does chip/package/board signal and power integrity.
Just like what Ansys/Apache Sentinel does. Lattice uses Sigrity.
(booth 2616) Ask Brad Griffin. Freebie: Denali party tickets
Cadence Conformal Low Power does EC "from RTL to transistor level."
Insert overused empty vacuous adjective-rich marketing claims here.
(booth 2616) Ask Kenneth Chang. Freebie: Denali party tickets
PRIMETIME & RIVALS
5.) Cadence Tempus is Lip-bu's answer to Aart's PrimeTime STA monopoly.
50 M inst design in PrimeTime took 8.5 hours on 8 CPUs; Tempus did it
in 58 min on 32 CPUs. Tempus does 100 M paths per hour vs. PrimeTime
60 M paths per hour. Now generates legalized placement directives in
MCMM timing optimization while meeting 20/16/14 nm placement rules.
"No need for a placement tool to legalize ECO's, it's a big boy."
Claims 100 M instances per hour. TSMC certified for 20 nm and 16 nm.
Users Texas Instruments, Freescale, Maxlinear, ST Micro, NXP, Sharp.
(booth 2616) Ask for Ruben Molina. Freebie: Denali party tix
Synopsys PrimeTime is world's 95% marketshare STA tool. Also does
noise analysis. This year focused on "physically-aware ECO timing
and power: 3X faster TAT, reduced total power." ARM, AMD, Fujitsu,
Nvidia, Rambus are all talking at the PrimeTime SIG on DAC Monday.
(booth 1133) Ask for Robert Hoogenstryd. Freebie: pens
CLKDA Variance FX generates full arc/load/slew timing derate tables
based on process, temp, voltage, constraints -- 2 hours for 1000
cells per PVT corner. Now does non-Gaussian variance support and
early & late sigma generation -- others assume Gaussian variance!
Derates for PrimeTime, Tempus, ICC, First Encounter, ATOP, Olympus.
AOCV/POCV/SOCV/LVF 20/16/14 nm. Mediatek, Samsung, Qualcomm users.
(booth 1433) Ask for Isadore Katz. Freebie: tablet stylus
Excellicon ConStar displays large volume STA data plus SDC data
like unconstrained/paths, etc. Path analysis through waveforms.
(booth 2406) Ask for Himanshu Bhatnagar. Freebie: baseball cap
BUGHUNTERS
6.) NEW! -- Mentor Visualizer Debug Environment is Wally's debug answer
to Cadence SimVision/Debug Analyzer and Synopsys DVE/Verdi, etc.
It debugs RTL, gates and testbenches, automatic tracing to "pinpoint
original cause of errors; protocol and transaction-level debugging."
Does UVM, System Verilog, low-power UPF debug. Does this it both
interactively or post-simulation inside of Questasim and Veloce.
(booth 1733) Ask for Dave Rich. Freebie: Lego kits
CDNS JasperGold is showing Coverage App that does formal linting
of your RTL. X-Propagation App formally finds "X optimism" and
"X pessimism". Their Low Power App measures UPF/CPF power intent,
clock-gating, retention optimization and partial retention checks.
Their Secure Datapath App formally finds data leaks in your chip.
To check your ECO's are OK use Sequential Equivance Checking App.
Jasper customer party at Treasure Island this year! Busses are
at 11:30 AM SHARP on DAC Tuesday outside of Hall B at Moscone.
(booth 2033) Ask for Kathryn Kranen. Freebie: tote bag
MENT Questa Formal does CDC, X-checking, automatic RTL checks, formal
coverage closure, automatic property generation, connectivity checks,
CSR verification, protocols, plus sequential equivalency checking.
Users are Mediatek, AMD, Microsoft, Oracle Labs, Rockwell-Automation.
(booth 1733) Ask for Mark Eslinger. Freebie: Lego kits
Atrenta BugScope generates white-box assertions to catch coverage
holes, IP integration errors, and deep-cycle bugs and CDC errors.
Managers love it cause it test grades your daily/weekly regression
suites for module-specific sanity checks for your RTL changes.
Users ST Micro, Marvell, Renesas, Freescale, TI, NTT, Canon, LG.
(booth 1933) Ask for Yunshan Zhu. Freebie: USB charger
OneSpin 360 DV Quantify does full blown property checking, but uses
new coverage which "checks the checks" to direct the assertions at
uncovered areas. Beats regular sim stimulus coverage, so if a
problem exists, your checkers will see it. Infineon, Bosch, Maxsim.
Their 360 DV Inspect combines linting with property checking, user
doesn't have to write any assertions! Their 360 EC-FPGA does
equivalency checking RTL vs. post-synthesis netlists for FPGA's.
(booth 1219) Ask for Raik Brinkmann. Freebie: Frisbee thingy
Avery PropSYN does assertion synthesis for baseline verif. metrics.
Extracts microarchitectures. "Over 15 microarchitecture functions
and 60 assertions and cover properties". Pragmas. Hitachi uses it.
(booth 1225) Ask for Chris Browy. Freebie: LED flashlight
Atrenta SpyGlass Constraints does formal false path, MCP, and clock
intent verification, SDC validation, SDC equivalence check so your
constraints are in sync with evolving design/SDCs and incremental
SDC generation. A big selling tool. Renesas, Fujitsu, TI, ST, ARM.
(booth 1933) Ask for Mark Baker. Freebie: USB charger
Real Intent Meridian CDC is 25% faster, 35% more capacity for flat
analysis; new billion-gate hierarchical verification; new analysis
reporting with advanced customization and new scripting. "Does
500 M gates of RTL in 9 hours WITHOUT the suspect abstraction-
modeling SpyGlass & Questa use." Nvidia, Western Digital, Lantiq.
Their Ascent Lint has 46 new rules, new CDC readiness checks; works
with MathWorks HDL Coder synthesis and Calypto Catapult synthesis;
hierarchical waiver management and new report customization.
(booth 1825) Ask Sarath Kirihennedige. Freebie: a rose
NEW! -- Blue Pearl Advanced Clock Analysis lets engineers visually
verify and get CDC guidance automatically. Helps with clock setup
and checking. "Graphical representation of FSMs, CDC and false path
viewers with cross probing to RTL, schematic representation of RTL
with forward and reverse tracing, and linting message filtering."
Marvell, Microsoft, Harris, Teradyne, Ciena, Xilinx, Samsung, NEC.
(booth 832) Ask for Shakeel Jeeawoody. Freebie: squeeze balls
Ausdia Timevision-CDC does "block/fullchip CDC analysis on RTL or
gates using SDC constraints only -- so it can verify your actual
clock groups as being CDC-safe. Chips of 20 M to 500 M inst with
1000 clocks in 8 hours. New GUI user interface with full tracing.
(booth 1507) Ask for Sam Appleton. Freebie: squeezy ninja doll
Atrenta SpyGlass CDC does "protocol independent CDC checks for
control, data, and reset signals" and "CDC for data loss, glitch
hazards, data stability, re-convergence, and FIFO issues." LSI,
Qualcomm, TI, ST, Panasonic, Infineon, Ericsson, Cisco uses it.
(booth 1933) Ask for Ravindra Aneja. Freebie: USB charger
Aldec ALINT does CDC rule checking. Viewer shows violating code.
(booth 1521) Ask for Ajay Pradhan. Freebie: clock
FishTail Confirm formally verifies design constraints. This year
does "better signal-to-noise ratio versus our rivals. Our formal
engine only reports *real* issues to customers." Users are Altera,
Qualcomm, Xilinx, TI, Broadcom, Freescale, Xilinx, and Cypress.
(booth 1725) Ask for Ajay Daga. Freebie: none
Ausdia Timevision also formally verifies design constraints. Does
gate-level and RTL SDC. 20-80M inst, with 1000+ clocks in 8 hours.
Adding fully incremental & SDC promotion/demotion. Full hierarchical
matching tricky block boundary conditions. Maxim, AMCC users.
(booth 1507) Ask for Sam Appleton. Freebie: squeezy ninja doll
Excellicon ConMan formally generates design constraints. Does
multi/merged mode hierarical SDC's for synthesis, P&R, STA tools.
Extracts all root and generated clocks, clock groups, exceptions
(FP, MCP's max/min delays), IO's with related clocks budgeting
and case analysis values. Promotion/Demotion. New FPGA support.
Their ConCert verifies Tcl/SDC timing constraints. 350 M inst.
(booth 2406) Ask for Himanshu Bhatnagar. Freebie: baseball cap
FishTail Focus merges multi-mode PrimeTime STA constraints into one
single super mode. "STARC benchmark 4 M inst netlist with 18 modes.
We merged all 18 modes into a single super-mode. Timing correlation
100 psec pessimism & 10 psec optimism. Cut PrimeTime runtime 90%."
Now does DC, ICC, Cadence EDI, ATOP. TI, Cypress, Broadcom, Altera.
(booth 1725) Ask for Ajay Daga. Freebie: none
Real Intent Ascent IIV -- 50% faster on designs up to 250 K gates,
New FSM transition checks and state debugging; deeper root cause
analysis for FSM's. Ascent XV does X-propagation verification
and optimization. It now ranks X-sources and x-sensitive nets by
failure importance; deeper initialization audits; 10X faster
optimization of minimally correct reset schemes; smarter reporting.
(booth 1825) Ask Lisa Piper. Freebie: a rose
Avery SimXACT automatically find X bugs in RTL and eliminates false
X's in gate-level simulation. New X-verification of low power
designs, new X trace analysis and sequential backtrace reporting,
new pseudo SDF generator to resolve gate-level race conditions.
(booth 1225) Ask for Chris Browy. Freebie: LED flashlight
Synopsys Verdi 3 is the wildly popular design debug waveform viewer
with a Qt-based GUI. Aart got it with SpringSoft. Man, it does
everything! UVM, OVM, System Verilog, VHDL, SVTB, VMM, SVA, CDC,
FSBD, UPF/CPF, nWave, nSchema and TFV, PDML, CTS, SDC, STA, HW/SW.
(booth 1133) Ask for Thomas Li. Freebie: pens
VIRTUOSO & RIVALS
7.) Virtuoso Layout EAD does real-time in-design fast RC extraction.
Random walk capacitance solver, EM checking, finite-element mesher
for resistance, current limit/budget checks. Also does parasitic
re-simulation of partially completed layouts. Layout engineer gets
immediate feedback on layouts to avoid "rip and repair" syndrome.
(booth 2616) Ask for John Stabenow. Freebie: Denali party tix
Virtuoso IPVS does on-the-fly signoff DRC checks as you design. It
now does DPT odd loop detection with fixing hints for designers at
16/14 nm FinFET/FDSOI flows. Annotation Brower does cross probing.
Renesas, Cortina, ST uses IPVS. (booth 2616) Ask for Manoj Chacko.
NEW! -- Pulsic Animate does auto layout of analog (transistor level)
designs, with no constraints, no scripting, no programming required.
Multi-threaded. Makes 100's of fully PnR-ed layouts in minutes from
an OpenAccess schematic (vs. 2-3 weeks single layout in Virtuoso).
Polymorphic to create layouts instantaneously. NOT do serial tasks
like placement, then routing, etc. LIVE not canned super fast demo.
(booth 1713) Ask for Keith Sabine. Freebie: stuffed owl
NEW! -- G-Analog G-Toolbox is a custom circuit design toolbox with
50 GUI-based programs for input setup, output analysis, optimization,
characterization, post-layout, reliability. TCL/TK to customize.
They also have G-Migration for layout migration and prototyping.
(booth 200C) Ask for Jeff Tuan. Freebie: hard candies
Synopsys Custom Designer and Laker are Aart's two different answers
to the CDNS Virtuoso monopoly. Fujitsu, Renesas and TSMC are users.
(booth 1133) Ask for Dave Reed. Freebie: pens
Tanner EDA sells OA-based S-Edit schematic capture, L-Edit custom
layout, HiPer Verify DRC, and T-Spice SPICE. New IPL frontend PDKs.
New AMS-focused digital place and route tool "HiPer P&R". Founded
1988. Known for "cost effective" pricing. Not bad for cheap seats.
(booth 1701) Ask for Jeff Miller. Freebie: none
Symica AMS Design Suite is like Tanner EDA but has only three years
in business and it's based in Kiev. "007: From Russia With Love"
(booth 813) Ask Sergey Makarov or Vlad Potanin. Freebie: none
NanGate Library Creator fine tunes std cells for slow transitions,
power, voltage. Also multi-bit cells (saves 25-30% dynamic power,
20-25% leakage), CPU/DSP datapath (8-14% less area). 20/16/14 nm.
(booth 2409) Ask for Jens Michelsen. Freebie: none
ClioSoft Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Does hierarchical.
Work with DesignSync & IC Manage. Now option to suppress cosmetic
changes. Batch mode to run diffs in the background and save state
for later use or export to text format. Infineon, Qualcomm, Bosch,
Northrup, Marvell, Toshiba, TSMC, Analog Devices, Lattice, Vitesse.
(booth 2425) Ask for Karim Khalfan. Freebie: magnetic dart board
MunEDA Migration migrates analog/mixed-signal/RF circuits between
different foundries/processes. Includes schematic migration
(symbols/terminal/properties), resizing, optimization (specs,
constraints, aging, low power), and verification for robustness.
(booth 2213) Ask for Michael Siu. Freebie: mouse pads
ClioSoft SOS RF does design data management DDM for RF engineers
using the the Agilent Advanced Design System (ADS). No one else
does that! It does enterprise-wide revision control, DDM and
multi-site support. Triquint, RF Micro Devices, MIT Lincoln Labs.
(booth 2425) Ask for Amit Varde. Freebie: magnetic dart board
RTL SIMULATORS
8.) MENT Questa Platform bundles all Mentor Verilog/VHDL RTL simulation,
emulation, low power, VIP, traffic generators, interconnect test,
intelligent testbench, coverage, UVM, and formal into one big smudgy
bundle that keeps MENT Sales happy when competing against SNPS and
CDNS. "But does it have 123?" "Hell, yes! Plus 456 and 789 too!"
(booth 1733) Ask for Tom Fitzpatrick. Freebie: Lego kit
CDNS Incisive Platform bundles all the Cadence RTL simulation stuff
yada, yada, yada... This year claims "10x faster SV constraint
engine, patent-pending x-propagation, low-power, new UVM-ML, 20X
faster formal analysis, new register validation app, new UVM debug,
30% better Specman "e" debug time, 10x better debug database size."
(booth 2616) Ask for Bill Winkeler. Freebie: Denali party tix
SNPS Verification Compiler bundles all the Synopsys simulation stuff
yada, yada, yada... The funny thing is they're trying to pass this
off as "new" when it's just a bundling of prior existing SNPS tools.
("Exactly how dumb does SNPS Marketing think their customers are?")
(booth 1133) Ask for David Hsu. Freebie: pens
Rocketick RocketSim loads your Verilog source into 100's of GPUs and
runs as 23X faster co-sim to CDNS Incisive, SNPS VCS, MENT Questa.
This year showing RocketSim-CPU which runs CPU's instead of GPU's.
"Compile 1 billion-gate design in 2 hours." 4-state-logic for X.
(booth 901) Ask Uri Tal. Freebie: USB keys
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
New Plot Viewer does simple/polar/vector graph and image/color map.
(booth 1521) Ask for Sunil Sahoo. Freebie: clock
Defacto Star Design tools is an 8-part unified RTL design flow where
coherency between Verilog/VHDL RTL, SDC, IP-XACT, UPF, and SystemC
is guaranteed. Builder does RTL design editing and exploration.
Checker does simulation-free connectivity checks. Low Power does
UPF design exploration. Other parts do padring, DFT, IP, etc. See
review in ESNUG 530 #2. Users Qualcomm, Broadcom, Intel, Maxim-IC.
(booth 807) Ask for Chouki Aktouf. Freebie: swiss army knife
Amiq DVT Eclipse IDE provides IDE for design and verification
languages like "e", System Verilog, VHDL. Visual C like stuff.
Their new Specador automatically generates HTML documentation.
(booth 1214) Ask for Cristian Amitroaie. Freebie: none
NEW! -- Agnisys DVinsight is a friendly editor for UVM developement
sort of like Amiq. Helps your write code. And their IDesignSpec
converts specifications for Registers/Sequences into UVM/RTL. NASA,
Intrinsix, Inphi, Violin Memory, HGST, Mercury Computers, Icron,
Barclays, Conexant, Wipro, Conexant, John Deere, CERN uses it.
(booth 608) Ask for Anupam Bakshi. Freebie: beer bottle opener
Verific sells System Verilog and VHDL parsers with C++ interfaces to
EDA developers. Perl interface. Parsers for UPF 2.1, PSL, EDIF.
Synopsys, Atrenta, Xilinx, Altera, AMD, Freescale, Infineon users.
(booth 1909) Ask for Michiel Ligthart. Freebie: stuffed giraffe
SYNTHESIS
9.) Mentor bought out Oasys RealTime Designer. It's RTL estimation,
synthesis, floorplanning, design partitioning, and pre-CTS opto
all now on top of MENT's MCMM Olympus-SoC P&R tool. Intel, TI,
Broadcom, Juniper, Qualcomm used Oasys. Xilinx Vivado is Oasys.
MENT also gets RealTime Floorplan Compiler which takes RTL for
entire chip for quick floorplan that "meets timing, power, area,
physical constraints" and "4-6 weeks floorplaning now 2 days!"
It's like Wally's estimation answer to Cadence First Encounter.
(booth 1733) Ask for Sudhakar Jilla. Freebie: Lego kit
Cadence RTL Compiler does physically-aware, low power optimized
synthesis of Verilog RTL to placed-gates. Rivals Design Compiler.
Better correlation to P&R. 50% shorter timing, power cut 15%, area
cut 10%. 1.7x faster from parallelization. Re-architected to be
power-intent agnostic and 20x faster with a streamlined use model
plus a re-visioned multi-Vt flow for power/area/timing tradeoffs.
CDNS RTL Compiler is used by TI, IBM, ARM, ST, Freescale, Canon,
Apple commonly in a dual synthesis flow with SNPS Design Compiler.
(booth 2616) Ask for David Stratman. Freebie: Denali party tix
Synopsys demoing both DC Explorer and Design Compiler Graphical.
Claims "10% smaller area plus reduced congestion and leakage."
(booth 1133) Ask for Gal Hasson. Freebie: pens
Atrenta SpyGlass Physical helps RTL designers create floorplans
for their chips pre-synthesis. It's similar to SNPS DC Explorer.
Early detection of area/timing/congestion issues. Does critical
signals, bus fabric, clock distribution, connectivity, etc.
Qualcomm, Canon, Hitachi, Renesas, TSMC, ST, Texas Instruments.
(booth 1933) Ask for Mark Baker. Freebie: USB charger
VERIFICATION IP
10.) Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
- have VIP for "AMBA 5 CHI, eMMC 5.0, HDMI 2.0, LPDDR4, MIPI C-PHY,
MIPI CSI-3, MIPI SoundWire, Mobile PCI Express, PCI Express Gen 4,
USB SuperSpeed Inter-Chip, Wide I/O 2"
- a Denali-style API, all simulated VIP now runs on VCS, Questa and
Incisive. "VCS or Questa customers do not need Specman e, as
support for the e language is built into our simulator interface."
- TripleCheck, their IP validation tool is in its 3rd rev.
- "We have assertion-based VIP for the AMBA protocols and OCP."
"Do you support 123?" "Yes, plus 456 and 789!" Apple, ARM, Broadcom,
HP, IBM, Intel, LSI, Hitachi, Marvell, Qualcomm, Samsung, AMD, ST.
(booth 2616) Ask Frank Schirrmeister. Freebie: Denali party tix
Avery Verification IP (VIP) for SSDs and embedded flash mem, UFS 2.0,
Unipro 1.6, Soundwire, PCIe 4.0, eMMC 5.X, UHS-II, DDR4, LRDIMM,
HMC, and CAN FD. Seagate, Samsung, Broadcom, Western Digital users.
(booth 1225) Ask for Chris Browy. Freebie: 4-in-1 flashlight
Arrow JEDEC UFS VIP does related BFMs -- JEDEC UFS 2.0 Host, JEDEC
UFS 2.0 Device, MIPI Unipro 1.6/1.4, MIPI MPHY 3.0 -- and a full
testbench for compliance, random test-suits, coverage, assertions.
Their USB Validator Suite does full USB 3.0 compilance. SW API.
(booth 715) Ask for Aditya Mittal. Freebie: none
SmartDV VIP claims 70+ VIPs. God knows what, though. (booth 411)
Mentor Verification IP (VIP) competes in this space, but they don't
seem to be showing it at this DAC.
Synopsys Discovery Verification IP (VIP) competes in this space, but
they don't seem to be showing it at this DAC.
CALIBRE & RIVALS
11.) Calibre nmDRC has 40% runtime improvement and 50% memory reduction.
Same rules, same data, same hardware, updated Calibre version only.
While 14/16 nm new for P&R, it's old hat for Calibre. 10 B devices
and full reticle sized designs done 9.6 hours overnight. MENT now
working on 10 nm. Triple patterning, Self-Aligned Double Patterning
(SADP), hot spot pattern matching detection, voltage aware spacing.
It's golden DRC/LVS sign-off of Samsung, TSMC, GlobalFoundries, UMC.
(booth 1733) Ask for John Ferguson. Freebie: Lego kit
Calibre RealTime lets engineers do instantaneous sign-off DRC during
layout creation inside ICC (ESNUG 538 #4) and Laker (ESNUG 529 #4).
"Same deck, same results as batch Calibre." Does double patterning,
pattern matching, voltage-aware DRC, and density checks -- just like
"batch" Calibre. Claims "2X productivity" at 20/16/14 nm.
(booth 1733) Ask for Srinivas Velivala. Freebie: Lego kit
Cadence PVS does double patterning, 3D-IC, FinFET and FD-SOI device
extraction, reliability checking and constraint validation. Like
Calibre and ICV, PVS does similar "in-design" DRC/LVS in CDNS EDI.
(booth 2616) Ask for Manoj Chacko. Freebie: Denali party tix
NEW! -- EDXACT Belledonne compares layout versus layout, finds quickly
differences with respect to the wiring, and it tells if diff important.
(booth 527) Ask for Mathias Silvant. Freebie: pens
NEW! -- DRC-DA SwarmDRC distributes long DRC runs on 1000's of CPU's
in their private cloud. One billion gate DRC in 1 hour vs. 1 day.
(booth 428) Ask for Ian Tsybulkin or Maxim Kharchenko.
Sage iDRM is a physical design rule compiler. Enter your design rule
into its GUI and iDRM finds all the places in your physical design
where that rules applies -- plus where it's been violated. It helps
make sensible DRC decks. DRVerify does DRC runset verification. It
generates test cases systematically covering all boundary conditions
of that design rule. The result is a GDSII file that displays all
passing cases and failing cases. You now run your under-development
DRC deck (e.g. Calibre, ICV, PVS decks) on this GDSII file and the
DRC should flag all the failing cases and none of the passing ones.
Any deviation from that indicates a mismatch and a possible bug in
your DRC deck. DRM2PDK auto generates Pcell physical parameters.
(booth 1423) Ask for Coby Zelnik. Freebie: none
Coventor SEMulator3D is a tool for the fabs themselves to simulate
the manufacturing process. Virtual fabrication. Model etching of
multi-material stacks with redeposition (passivation), sputtering
(physical etching), and etch bias (lateral or chemical etching).
(booth 718) Ask for David Fried. Freebie: none
Synopsys IC Validator does DRC's locked inside ICC/ICC2. It's
not a standalone tool -- and it's not being focused on at this DAC.
MARGINs & ECOs
12.) Dorado Tweaker is a family of physically-aware ECO tools:
Funct. ECO / Timing ECO / Power ECO / Metal ECO / Clock ECO
Tweaker-F1 / Tweaker-T1 / Tweaker-P1 / Tweaker-M1 / Tweaker-C1
Synopsys PrimeTime-ECO vs. Tweaker-T1
Cadence Conformal-ECO vs. Tweaker-F1
Static/dynamic power ECO's. 50 M inst. 16/14 nm FinFET designs.
Broadcom, Qualcomm, LSI, LG, TSMC, Mediatek, Samsung, Altera users.
(booth 2013) Ask for JJ Hsiao. Freebie: magic ball
ICScape TimingExplorer is a physically-aware MCMM timing ECO tool.
Now does PBA-based timing fixes, and route-based timing fix. And
their ClockExplorer does CTS clock analysis/constraint generation.
(booth 1005) Ask for Jason Xing. Freebie: LED flashlight
Cadence Conformal ECO Designer this year tersely claims it does
"fine grain control". Ok... Broadcom, Qualcomm, Cisco, Fujitsu.
(booth 2616) Ask Kenneth Chang. Freebie: Denali party tix
Arcadia TimeHawk does STA for ECO's. Cut ECO backend iteration
time by 50%. Utility scripts, new GUI, to build a MCMM flow.
(booth 727) Ask for Joey Lin. Freebie: flying disc
Synopsys PrimeTime ECO is chatting up ECO's at DAC this year.
(booth 1133) Ask for Robert Hoogenstryd. Freebie: pens
IP TOOLS
13.) IC Manage GDP IP Pro maximizes your internal IP reuse -- it can be
a mix of homebrew and purchased IP. Trace bug dependencies. Fixes
across all IP revs and designs. Bug history viewable. Checklist
driven design, testbench reuse. Broadcom, Nordic Semi, Samsung.
(booth 2413) Ask for Anthony Galdes. Freebie: chocolates
Methodics ProjectIC does IP lifecycle management. From creation
through to integration. Release management, usage tracking, plus
parent/child relationships), and a dynamic IP catalog for engineers.
(booth 1407) Ask for Vishal Moondhra. Freebie: none
Atrenta SpyGlass IP Kit checks soft IP for problems, plus definitions
of the rules to run, scripts to automate the process, documentation,
and a test design to make sure everything is installed correctly.
Checklist design of IP. Linting, CDC, power, DFT, and physical.
TSMC, ST, TI, ARM, Ceva, Sonics, Arteris, DMP, Imagination, PLDA.
(booth 1933) Ask for Kiran Vittal. Freebie: USB charger
NEW! -- Mentor Novelics MemQuest is Wally's answer to SNPS DW Memory
Compilers. It's a web-based custom memory IP generator optimized for
low dynamic power, low leakage, high density, speed memories. Auto
self-repair, auto leakage reduction, and "routing-friendly" memory
IP generation. Single or multi-PVT corners. MUXing and banking.
(booth 1733) Ask for Farzad Zarrinfar. Freebie: Lego kit
Interra MC2 Memory Compiler creates physical memory architectures,
characterization flow and generation of specific memory instances.
(booth 204C) Ask for Vijeta Kashyap. Freebie: USB drives
Atrenta GenSys Assembly does IP integration, chip assembly, automated
RTL generation. Competes vs. Synopsys CoreAssembler or Duolog Weaver
of Magillem Platform Assembly. Claims 20-30X faster than IP-XACT.
"Integrate 64-bit ARM Cortex cores in your chip in days, not months."
TI, Sandisk, Broadcom, ST Microelectronics, LG, Canon, Renesas.
(booth 1933) Ask for Kiran Vittal. Freebie: USB charger
FABS
14.) TSMC clearly owns 28 nm. The big tech battle then was gate-first
vs. gate-last and Hsinchu chose wisely. Now the fight is 20 nm.
And the big tech question is TSMC FinFET vs. Samsung/ST FD-SOI?
(booth 1801) Ask for Suk Lee. Freebie: pens
Samsung, that tiny fab that made $1 billion worth of Apple chips
(booth 819). Ask for ???. Freebie: none
Intel 14 nm is the one thing that strikes true terror in the hearts
of all the other fabs -- their fear is they'll be at the one trade
show where Intel finally shows it off -- and steals their customers.
(booth 1607) Ask for ??? Freebie: empty TSMC/GF/Samsung booths
TowerJazz does iPDK's for its volume 130 nm digital & AMS customers.
(booth 1301) Ask for David Postula or Russell Ellwanger.
MOSIS combines many companies' designs into one wafer run for low
volume and prototyping production. GF, IBM, TSMC. (booth 1207)
CMP does prototyping and low volume IC production. CMOS, SiGe,
BiCMOS from ST. 28 nm FD-SOI GloFlo 3D-IC. (booth 2012)
WORKSPACE & DESIGN DATA MANAGMENT
15.) IC Manage Views lets engineers get their EDA tools populated on their
desktop very quickly. Claims "1 gigabyte, 10,000 file work-space
in 1 second to populate." Broadcom benchmark saw 2 GB in 15 sec.
Their GDP does data management for digital and custom designers to
find, modify, release and track design data through to tapeout. Now
multi-site support with 10X faster remote site performance. Samsung,
Altera, AMD, Maxim, Nvidia, Broadcom, Nordic Semi, CSR are users.
(booth 2413) Ask for Alex Tumanov. Freebie: chocolates
ClioSoft SOS does HW configuration management and rev control for
Virtuoso, Laker, Pyxis, Custom Designer, Agilent ADS. Built-in IP
management and reuse. Does soft integrations with in-house flows.
ADI, Dongbu, Huawei, Lattice, Oracle, Marvell, Toshiba, TSMC users.
(booth 2425) Ask for Karim Khalfan. Freebie: magnet darts
Methodics VersIC from Missing Link acquisition. Users request a
release from Cadence or Synopsys UI. Release candidate must be
verified and released only if it passes quality tests. Then added
IP repository. Stops bad release bringing whole design team down.
NXP, Cirrus, Cisco, Samsung, Google, Huawei, Microsoft, Boeing.
(booth 1407) Ask for Vishal Moondhra. Freebie: none
Runtime FlowTracer automates your design flow across 1000's machines.
Compute farm record 1.5 M jobs, 18 M files in 1 single customer flow.
License and network montoring products, too. Competes vs. LSF/GRID.
New LicenseAllocator does fair share on multiple sites dynamically.
(booth 1625) Ask for Andrea Casotto. Freebie: stuffed foxes
SystemC/C/C++ STUFF
16.) Cadence C-to-Silicon takes in untimed SystemC and gens Verilog RTL
that Design Compiler and RTL Compiler can easily digest. Users are
Casio, Freescale, Fujitsu, Ikegami, Sunplus. Forte Cynthesizer
at CDNS now. Its users Samsung, LG, Sony, Realtek, Toshiba, Ricoh.
Now the big question is how will Cadence combine these two C tools?
(booth 2616) Ask for Phil Bishop. Freebie: Denali party tix
HOLY CRAP! -- Calypto Catapult synths SystemC/C/C++ to Verilog RTL
and Google uses it! ("How the *BLEEEEEEEP* did they snag GOOG???")
It does pure C++ and SystemC, low power, ECO plus integrated formal
SLEC-Pro equivalency checking. New Catapult Catware synthesizable
IP which is SystemC and C++ parameterizable source code for 25 FFT
and filters. Back-annotate area/timing from Design Compiler. Gets
10-30% less area. Ericsson, Fujitsu, Hitachi, ST Micro, Toshiba.
(booth 2333) Ask for Bryan Bowyer. Freebie: M&M's and tatoos
Calypto SLEC does SystemC/C++/C-to-RTL functional equivalence. Tight
EC with Catapult; less tight with Forte or C-to-Silicon. Also does
C++ assertion/property checks. It's the only known C-to-RTL EC tool!
(booth 2333) Ask for Thomas Bollaert. Freebie: M&M's and tatoos
NEC CyberWorkBench does C/SystemC into Xilinx/Altera FPGAs. Has low
power and auto architecture exploration. Both control intensive and
data dominant designs. Debugging can be done early in C/SystemC.
Toshiba, Panasonic, Renesas, Mitsubishi, Fujitsu, Hitachi, Renesas.
(booth 1521) Ask for Kazutoshi Wakabayashi. Freebie: trick game
Synopsys Virtual Development Kit is a microcontroller-based virtual
system test bench for automotive safety standards simulations.
(booth 1133) Ask for Marc Serughetti. freebie: pens
Cadence Virtual System Platform lets you write and debug SystemC
models that run screaming fast -- even faster on Palladium and RPP.
Competes vs Synopsys Virtualizer, Mentor Vista, Carbon SoC Designer.
(booth 2616) Ask Frank Schirrmeister. Freebie: Denali party tix
Fraunhofer COSIDE is a system level tool based on SystemC as well
as on SystemC AMS 2.0. Competes vs. Matlab Simulink or MENT Vista.
(booth 709) Ask for Karsten Einwich. Freebie: cookies
Breker TrekSoC generates multi-threaded, multi-processor, multi-mem
C test cases to verify embedded SoCs. New integration with SNPS
Verdi debug. Users Broadcom, IBM, Nvidia, ST Micro, ST-Ericsson.
(booth 2602) Ask for Tom Anderson. Freebie: none
Carbon Performance Analysis Kits are pre-built virtual prototypes
and software for ARM Cortex-A9/A15/A7/A57/A53 emulation. Also has
CCI-400, DMC-400, GIC-400, NIC-301, etc." Competes vs. emulators.
Samsung, Broadcom, ST, Hughes, Freescale, Altera, Mediatek users.
(booth 1815) Ask for Bill Neifert. Freebie: none
Intel CoFluent Studio does HW/SW system modeling in "intuitive"
graphical notations written in ANSI C/C++ code. Intel uses it.
(booth 1607) Ask for Andy Grove. Freebie: paranoia
Magillem has a massive design environment based on IP-XACT and TLM
modeling that does RTL to DFT to UPF/CPF to I/O to documentation.
Intel, STM, TI , NXP, Samsung, LG, Altera, Qualcomm, Ricoh users.
(booth 325) Ask for Pascal Chauvet. Freebie: USB sticks
Duolog Socrates similar to Magillem. Massive IP design environment.
(booth 2019) Ask for David Murray. Freebie: Irish whiskey
Imperas does virtual platform based software development, debug and
test. Acceleration on multicore hosts. (booth 2001) Jim Straus
Codasip Framework is ASIP (application processor) dev environment
that generates a C/C++ compiler, debugger, synthesizable RTL and UVM
based verification. HUH??? (booth 2014) Ask Karel Masarik.
Synopsys Target MP Designer does parallelization of ANSI C code
across multiple distinct processors. Now works with IP Designer.
(booth 1133) Ask for Steve Cox. Freebie: pens
Interra Vega Media Analyzer does frame-by-frame analysis of videos
encoded HEVC/H.264/VP9/VP8 for standards compliance. (booth 204C)
TEST/SCAN/BIST/JTAG/FAULTS
17.) Mentor Tessent IJTAG does "efficient production test and support for
in-system Power-On Self-Test for ISO 26262 used in auto and other
industries." Most of Wally's test brainiacs rather be at ITC, but
if you find one at DAC, ask him/her to explain IJTAG. Neat stuff!
(booth 1733) Ask for Steve Pateras. Freebie: Lego kit
TSSI Solstice-TVT uses waveforms to shrink ATE pattern generation.
Reads IEEE P1687 IJTAG) and generates ATE-ready patterns for
Advantest/Teradyne/National Instruments testors. Simulating the
patterns on Verilog model of the target ATE box. AMD reduced
their test chip patterns debug loop from 2-4 months to 24 hours.
(booth 2001) Ask for David Leslie. Freebie: pens
Cadence Encounter Test and RTL Compiler Physical is Lip-bu's answer
to Mentor Tessent and Synopsys TetraMax. These two CDNS tools do
"physically-aware scan insertion and stitching-in during front-end
design enables less congestion, better area, and lower power." It
can restructure and reorder (where needed) your scan logic in P&R.
Users are: IBM, Texas Instruments, PMC-Sierra, Analog Devices Inc.
Cadence Encounter Test LBIST competes against Mentor Tessent LBIST.
For automotive devices. Safety standards ISO 26262 and AEC-Q100.
(booth 2616) Ask for Nitin Parimi. Freebie: Denali party tix
Atrenta SpyGlass DFT does "RTL analysis for stuck-at/at-speed
testablity, low power design, JTAG/IEEE1500" and "RTL fault coverage
estimation for stuck-at, transition and random-resistive faults."
Finds "hard-to-test" or "random resistive" faults -- faults that
cause low ATPG efficiency, long runtimes and large pattern counts.
Qualcomm, Samsung, Apple, TI, ST, Mediatek, Canon, Cisco users.
(booth 1933) Ask Kiran Vittal. Freebie: dual port USB charger
WinterLogic Z01X does RTL and gate-level fault simulation to report
test coverage (stuck-@, bridge, transition, IDDQ) of functional,
BIST and diagnostic test. Competes vs. Synopsys Certitude. New
fault viewer, TCL, 2X RTL. Qualcomm, Broadcom, Nvidia, Freescale.
(booth 1312) Ask for Jason Campbell. Freebie: gyro wheel
HARD & SOFT IP
18.) ARM Ltd is having its annual A-to-Z 16 dwarves orgy -- Ansys, Carbon,
Lauterbach, Sonics, Rambus, Tanner, Zolcalo -- plus Big 3: Synopsys,
Mentor, Cadence all taking turns in the money shots. (booth 2001)
ARM, Inc. 32/64-bit RISC CPU, mem IP, std cell libs. (booth 2007)
Synopsys sells Virage DW ARC 600 & 700 family of cores, plus Virage
mem IP, plus Virage InChip std cell libs that all directly compete
against ARM. 170 customers. DW ARC comes in low power and audio.
(booth 1133) Ask for Mike Thompson. Freebie: pens
Cadence IP Portfolio has interface IP for USB, PCIe, MIPI, Ethernet;
analog mixed-signal IP for SerDes, ADC, DAC, AFE, power management;
peripheral IP for I2C, I2S, PWM; Denali memory IP for DDR, LPDDR,
WideI/O, NAND Flash; Tensilica for baseband, audio, imaging/video.
(booth 2616) Ask for Martin Lund. Freebie: Denali party tix
Adapt-IP USB 3.0 IP is where Mac McNamara finally ended up! Built
with Cynthesizer HLS, which Mac ironically competed against when he
sold C-to-Silicon at CDNS. His BarScanner IP scans bar codes as
viewed by smart glasses wearer. Used by FedEx. (booth 2419)
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precision clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 1919) Ask for Mahesh Tirupattur. Freebie: none
CAST has a mess of 8051 cores, GPU and accelerator IP cores, CAN FD,
H.264 Video encoders, JPEG IP. (booth 1024) Ask Nikos Zervas.
Codasip Codix IP competes vs. TenSilica and ARC. 16-bit cacheless
DSP, 32-bit RISC, 6-stage 32-bit VLIW. (booth 2014) Karel Masarik.
Cortus SA sells ultra low power 32-bit microcontoller IP cores; four
types: RISC to floating point. (booth 2402) Ask Michael Chapman.
Ensilica Ltd. sells configurable 16/32-bit eSi-RISC, eSi-Crypto,
eSi-Comms, eSi-Connect. (booth 1401) Ask for Ian Lankshear.
PLDA sells IP for SuperSpeed USB, PCI Express, PCI-X, 10Gb TCPIP
for ASICs and FPGAs. (booth 201C) Ask for Vijay Polavarapu.
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". (booth 1101) Ask for Micke Wersall.
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180 nm to 28 nm. (booth 1701) As for John Maneatis.
Uniquify DDR4 IP has silicon of 2800 megabits per second (Mbps) in
TSMC 28HPM. Self-calibrating. (booth 1013) Mahesh Gopalan.
SEE YOU AT DAC
19.) If you're at DAC and you want to hook up to talk trash, on DAC Sunday
I'll be at Gary Smith's pre-DAC talk at:
Sunday 5:00-5:30 pm, Intercontinental Hotel, Grand Ballroom A
and on DAC Monday, I'll be moderating my DAC Troublemakers Panel at:
Monday 1:30-2:30 pm, Room 236/238, Moscone Convention Center
and later on DAC Monday night, Jim Hogan is hosting his annual
charity Hot Zone VIP party at:
Monday 6:30-??? pm, Slim's at 333 11th St., San Francisco
Anyway, I'll see you at DAC! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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