!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2016"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
You might want to print out a hardcopy of this as an unofficial guide to the
Austin DAC'16 exhibit floor. List is ranked in order of importance.
NEW SCHOOL RTL SIMULATORS
1.) Seeing anything in the Verilog RTL software simulator market change
is like going through an earthquake in Iowa. "WTF!!? We're in IOWA.
Earthquakes AREN'T SUPPOSED TO HAPPEN IN IOWA!" This year's #1 tool
for the DAC'16 Cheesy Must See List is easily:
Cadence RocketSim -- a bunch of Israeli EDA R&D guys have been killing
themselves over the past 9 year to work out the kinks in parallelizing
Verilog simulation into multi-threads on 100's of regular multicore
Intel x86 XEON servers. What they got benchmarked 23X faster vs. VCS,
Incisive, Questa. Does gate and RTL sims. Compiles 1 billion gates
in 2 hours. 4-state-logic for X. Full System Verilog and accelerates
SVAs -- and all this from last year before Lip-Bu bought Rocketick!
SNPS/CDNS/MENT have all had internal multithreading R&D projects for
over 5 years now -- and none have paid off. The only other tool in
this space was when MENT bought Axiom in 2013 and it didn't pan out.
"Only works for certain designs. Too many events overwhelmed it."
But then Lip-Bu bought Rocktick? Huh? What changed? Isn't this
broken technology? Which started me snooping...
Two things changed. The first was Uri Tal and his Israelis came up
with some clever way to get around that "too many events" problem
(which I do not fully comprehend.)
Second is Cadence "Project X". Before RocketSim could only access
VCS/Incisive/Questa through their PLI's -- which was a nasty choke
point. "Project X" is CDNS R&D natively compiling the RocketSim
source C together with the Incisive source C into one GNU C++ object
called "Xcelium" -- thus bypassing that PLI choke point! Now a
50 million gate synthesizable System Verilog RTL design (Little Boy),
Xcelium on 8 core Linux box ran 4X faster than Incisive on a single
core Linux machine. For a 400 million gate design (Fat Man),
Xcelium on 6 cores ran 9.3X faster. That is, the larger the design
with the most activity the testbench stimulus, the better speed-up
Xcelium got! When 400 M gate Fat Man was doing high activity DFT
gate-level simulation it was 30X faster. This 4x-9.3X-30X boost
revitializes the RTL SW market (or at least Incisive's share of it.)
(booth 107) Ask for Uri Tal. Freebie: Denali party tix
Synopsys Cheetah VCS is Aart playing catch-up with RocketSim; but
even according to the SNPS press release Cheetah is still 2 years out
and it's using Nvidia GPU's instead of the Intel x86 CPU's. And
I wonder if the too-many-events problem is what's taking 2 years?
(booth 149) Ask for Manoj Gandhi. Freebie: pens
SYNOPSYS DESIGNWARE & ARM CORTEX
1.5) This isn't the #2 "must see" -- but more of a public call out to both
Aart's DesignWare parts and Simon Segars's ARM Cortex/M0/Mali CPU/GPU
cores. In my DeepChip hard/soft/VIP IP survey, these two absolutely
dominated in the hard & soft IP sections. Dominated! (DAC'15 #9)
DIGITAL P&R
2.) My true #2 "must see" is about an IC Compiler II possibility.
Synopsys IC Compiler II -- ever since ICC2's launch in March 2014,
Aart's marketing machine has been projecting that ICC2 works and
was a "game changer". The problem is again and again I found that
IC Compiler II had tech issues from Day One (ESNUG 537 #10, 538 #1)
and onwards in (ESNUG 547 #7, 548 #1, 550 #1, 552 #6, 554 #3) that
looked especially bad since Aart was up on stage during those 27
months saying "ICC2 works! Honest!". On DAC Monday they're doing
an ICC2 lunch. I'd like to attend to see if Aart's R&D has finally
fixed ICC2's multi-databases/capacity/runtime/coloring problems.
This could be a major tipping point for IC Compiler II. Or not.
(booth 149) Ask for Antun Domic. Freebie: lunch
Cadence Innovus -- officially launched 15 months ago, is Anirudh's
attack on Aart's ICC/ICC2. Since then there was a major hush-hush
kerfluffle where Apple benchmarked it at 14/10nm against ICC2 and
then switched over to Innovus. (ESNUG 547 #7) Then Innovus won in
another TSMC 16FF+ user benchmark against ICC/ICC2. (ESNUG 550 #1)
Then 5 different PD engineers discussed Aart's patch rev of ICC2 of
Sept 2015, how Innovus works well at 16/14nm, and how Innovus thrives
on the "new double-/triple-/quadruple-patterning digital color layout
problem at 10nm that Aart's ICC2 can't handle." (ESNUG 552 #6)
Then Imec's world's first 5nm tapeout only used Innovus, Tempus,
Virtuoso, MENT Calibre -- no ICC/ICC2, no PrimeTime. (ESNUG 554 #3)
This year Anirudh's Innovus minions have been busy claiming "10-15%
better PPA using new Power Opt", "better placement QoR by 20% with
GigaPlace", and better parallel and distributed "for more capacity".
HiSilicon 20% less area. Toshiba 16% less area & 25% less power.
10nm/7nm. "Deep hooks into Virtuoso for your A/D chips, too!"
Qualcomm, Nvidia, ST, Faraday, HiSilicon, Broadcom, ARM, NXP users
(booth 107) Ask for KT Moore. Freebie: Denali party tickets
Mentor Nitro-SoC and Oasys-RTL -- are Wally's answer to Aart and
Anirudh in digital implementation. Oasys-RTL does crazy fast RTL
synthesis floorplanning, design partitioning, congestion analysis and
pre-CTS opto. 3 hours to synth & floorplan a 2 million inst chip
using 4G of machine memory. Can do 6 M inst flat. (ESNUG 560 #6)
Synthesized and floorplanned a 5.2 M inst customer chip flat, 16nm
TSMC, in 7 hours 48 minutes on a single thread. Does "place first"
where RTL is synthesized into a virtual physical partition and
optimized at RTL level. "Lets us do various What-If's that were
impossible before!"
This year Nitro-SoC claims 2.0M insts per 24 hrs, 5X CTS and placer
speedup, compact database, 5M inst block sizes. Dynamic area recovery
and FinFET power optimization gets "10% better area and power". Does
multi-patterning, native coloring, conflict resolution engines, direct
hooks with Calibre signoff. Abutted floorplanning with replication.
ST Micro, Samsung Nvidia, MediaTek, ImgTec are MENT Sierra/Oasys users.
(booth 949) Ask for Sudhakar Jilla. Freebie: USB cellphone charger
Atoptech Aprisa -- has new adaptive PnR flow to dynamically adjust
the internal parameters based on the congestion and timing to deliver
close-to-optimal runtime and QoR. "No more script tweaking for your
design style!". Certified for TSMC 16FFC, 10FF, ready for 7FF.
2X runtime improvement since DAC'15. Also new power flow claims
"now 10-20% less power for FinFET designs" vs. SNPS/CDNS/MENT PD.
Users Broadcom, Samsung, Cypress, Mellanox, Clariphy, Solarflare
(booth 1648) Ask for Daniel Maung. Freebie: USB memory stick
IR-DROP / NOISE / THERMAL / POWER
3.) NEW! -- Ansys Gear SeaHawk is Jolly's Gear R&D guys bringing those
much talked about Big Data techniques into the RedHawk IR-drop/EM
franchise. (ESNUG 554 #1) The funky thing is this Hadoop stuff
doesn't change the guts of Apache RedHawk itself -- it's more like
SeaHawk is now cleverly guiding and redirecting RedHawk to get the
best QoR. Claims are SeaHawk can reduce die size by 5%. Can do
quick in-design power grid weakness and connectivity analyses.
Runs 1 billion inst chip with TAT of 5 hours/server core. Scalable.
Now there are no RedHawk "hot spot" surprises because SeaHawk guided
it to Do The Right Thing during the massive IR-drop/EM run.
(booth 1449) Ask for John "Jolly" Lee. Freebie: stuffed dog
Ansys Apache RedHawk is full-chip/3d-IC power integrity analysis and
sign-off, transients, simultaneous switching noise package/PCB with
distributed processing. Scalable to 16-32 machines (128-256 cores).
"500M insts with 8B resistors while keeping flat simulation accuracy"
Vector-based and vectorless. Clock jitter. TSMC 16/10/7nm FinFET.
Their Pathfinder ESD does full-chip multi-domain, multipath electro-
static discharge analysis. Capacity 8B transistors with critical
path tracing to identify and fix stressed device junctions. Their
Totem does transistor power-noise-reliability analysis. 16/14/10/7nm.
Apache users Samsung, NXP, ST, LSI, Applied Micro, Nvidia, TowerJazz.
(booth 1449) Ask for Ravi Ravikumar. Freebie: stuffed dog
Cadence Voltus-DP is Lip-bu's attack on Apache/Ansys RedHawk. Does
full-chip signoff, IR-drop, Power-Grid-Views. Massively parallel.
1B insts over 100s of compute CPUs. It won two user benchmarks
against RedHawk in ESNUG 560 #3 and ESNUG 561 #1. Now does ECO's.
Works with Tempus and Sigrity chip/package/board and Innovus PnR.
Early Voltus user cut runtime 9 days to 1 day on a large ARM design.
Nvidia, NXP, ST, HiSilicon, ARM, TSMC, Spreadtrum, Marvell, TI, LGE.
Voltus-Fi does transistor-level noise/power signoff with Quantus QRC
and MMSIM inside Virtuoso. Both Voltus & Voltus-Fi are TSMC 10/7nm.
Apache Totem and Synopsys HSim-PWRA both compete against Voltus-Fi.
(booth 107) Ask for Jerry Zhao. Freebie: Denali party tickets
NEW! -- Teklatech FloorDirector does pre-CTS power integrity analysis
for lowest on-chip dynamic voltage drop. Then it fixes the problem!
Yield lower dynamic power, faster performance and lower area. 1st PD
tool I've seen fixes dynamic power issues. 28nm to 10nm users.
(booth 223) Ask for Christian Petersen. Freebie: Viking kisses
NEW! -- Silvaco InVar Prime does quick IR checks on FinFETs using only
layout data. Snoops out high IR-drop, high current density related
EM issues, etc. Does "point-to-point interactive resistance checks,
pin resistance mapping, and very fast What-If analysis iterations."
(booth 649) Ask for Alex Samoylov. Freebie: tin cup & golf balls
Magwel ESDi also does ESD analysis just like Apache Pathfinder ESD.
Checks all possible shunt paths during event; fewer false positives.
It can now handle chips as big as 10x10 mm^2 on up to 1000 pins.
(booth 1013) Ask for Olivier Dupuis. Freebie: none
Silicon Frontline ESRA also does ESD analysis like Apache Pathfinder.
(booth 1712) Ask for Yuri Feinberg. Freebie: none
Entasys Navis optimizes pre-RTL number and location of power pads to
meet your target IR-drop and SSO noise margins. Samsung, LG users.
(booth 1029) Ask for JJ Park. Freebie: pens
VIRTUOSO & RIVALS
4.) NEW! -- Virtuoso ADE is Tom Beckley's new ramp of the CDNS ADE from
the CDNlive'16 just two months ago. ADE Explorer is what was the old
ADE-L, but it has nominal/corners/sweeps/monte carlo/spec comparison
are now in one tool. ADE Assembler has multiple tests/statistical
(from GXL). Multi tests are not widely used, although popular in
some circles. The controversy is in ADE Verifier, Beckley is trying
to get circuit designers to do planning and design against design
goals in analog/custom design -- a very tough sell! (ESNUG 560 #1)
CDNS calls this "the next generation analog design environment"
because it "opens the door to analog electrical spec verification."
(booth 107) Ask for Steve Lewis. Freebie: Denali party tix
Virtuoso Advanced Node for 16nm, 16FF+, 10nm and early 7nm adopters.
Does SADP coloring and MPT. 200 CDNS R&D engineers been working on
this for 4 years. Helps FinFET layout, track based routing, row
definition. CDNS R&D talking on moving from planar to FinFET.
Their Virtuoso Analog Assisted Automation is about CDNS Modgens being
on canvas, has a new pattern editor, plus built-in custom routing.
(booth 107) Ask for Jeremiah Cessna. Freebie: Denali party tix
Virtuoso Layout EAD does real-time in-design fast RC extraction, but
with no LVS required. Random walk capacitance solver, EM checking,
finite-element mesher for resistance, current limit/budget checks.
Also does parasitic re-simulation of partially completed layouts.
Layout engineer gets immediate feedback on layouts to avoid "rip and
repair" syndrome. New for EAD this DAC is slotting and "electrically
driven" routing. Aart is trying to copy these Virtuoso EAD ideas
with his Custom Compiler, but he can't find any big Tier 1 buyers.
(booth 107) Ask for John Stabenow. Freebie: Denali party tix
NEW! -- Synopsys Custom Compiler is Aart's 2nd attempt on Lip-Bu's
Virtuoso monopoly. The 1st try was Custom Designer (which flopped.)
CC was launched at the recent SNUG'16 show. Custom Compiler is a
new full custom environment on top of the old Laker3 router plus the
Ciranova Helix plus "assistant features" so the user can generate
from a symbolic editor different layouts of the same circuit. Once
you choose the "right" layout the polygon editor outputs the Pycell
level implementation. It also has hooks into HSPICE and FineSim.
(booth 149) Ask for Dave Reed. Freebie: pens
Silvaco Expert is a hierarchical IC layout editor. Schmatic driven.
10 Gig GDSII loads in "minutes". Uses Calibre Interactive for DRC
"on the fly". Rapid pan/zoom. Equal Resistance Router. OA and
interop PDKs (iPDK) makes design migration easier. And WTF???!!
Silicon Creations uses it for 10nm FinFET? Silvaco doing 10nm?!?
Also Silvaco Clever 3D RC field solver BEOL/MEOL parasitic extract.
(booth 649) Ask Michel Blanchette. Freebie: tin cups & golf balls
Pulsic Animate does automatic layout of analog (transistor level)
designs, with no constraints, no scripting, no programming required.
Multi-threaded. Makes 100's of fully PnR-ed layouts in minutes from
an OpenAccess schematic (vs. 2-3 weeks single layout in Virtuoso).
Did a 40% reduction in cell block implementation time for Ricoh.
(booth 1439) Ask for Keith Sabine. Freebie: stuffed hedgehog
Mentor Tanner is OA-based S-Edit schematic capture, L-Edit custom
layout, and T-Spice SPICE. Founded 1988. "cost effective" prices.
New this year: old HiPer Verify DRC was replaced by Calibre DRC.
Also Pyxis stuff coming in, too. Aiming at MEMS and IoT markets.
(booth 1828) Ask for Jeff Miller. Freebie: pens
Analog Rails is custom layout, but skipped DAC? Ask Cliff Wiener.
NanGate Library Creator fine tunes std cells for slow transitions,
power, voltage. Also multi-bit cells (saves 25-30% dynamic power,
20-25% leakage), CPU/DSP datapath (8-14% less area). 20/16/14/10nm.
This year: coloring, self aligned MOL, template based cell creation.
(booth 442) Ask for Jens Michelsen. Freebie: pens
LibTech LibChar does std cell, IO, SRAM characterization & modeling.
(booth 743) Ask for Mehmet Cirit. Freebie: none
NEW! -- Silvaco AccuCore XT does automated SRAM setup and hold, delay
and slew characterization. 5.5M element FinFET SRAM. (booth 649)
ClioSoft Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Does hierarchical.
Work with DesignSync & IC Manage. Can suppress cosmetic changes.
Batch mode to run diffs in the background and save state for later.
Infineon, Qualcomm, Bosch, Intel, Marvell, Toshiba, TSMC, Vitesse.
(booth 519) Ask for Karim Khalfan. Freebie: picnic blanket
MunEDA WiCked SPT converts analog/mixed-signal/RF circuits across
different foundries/processes. Transistor resizing, optimization,
and verification for best performance, area, low-power/low-voltage,
robustness against process variation and mismatch. Qualified for
FinFET, Bulk, Bipolar, BiCMOS, and FDSOI. ST, GF, SMIC, HLMC users.
Their WiCked Circuit Suite does transitor resizing for PPA, too.
(booth 1438) Ask for Michael Pronath. Freebie: tote bags
NEW! -- ICScape Skipper does fast layout review, analysis, debug, and
layout IP protection. 1TB GDSII. Marvel, Hisilicon, SMIC, Sandisk.
(booth 738) Ask for Jason Xing. Freebie: car tool kit
Keysight ADS and GoldenGate is for silicon RFIC design & simulation
New iPDK PyCell & TSMC iRCX support, more intuitive layout, does
electro-thermal on windows, harmonic balance & circuit envelope
converges faster. Qorvo, Skyworks, Broadcom/Avago, Qualcomm users,
(booth 727) Ask for Kaelly Farnham. Freebie: a tile?
ClioSoft SOS RF does design data management for RF engineers using
Keysight Agilent ADS. Northrop, IDT, Quorvo, Rohde & Schwarz, Inphi
(booth 519) Ask for Amit Varde. Freebie: picnic blanket
Intento ID-Xplore resizing/biasing/migration of analog/AMS circuits.
(booth 329) Ask for Ramy Iskander. Freebie: stickers
SystemC/C/C++/TLM STUFF
5.) Badru, Man with a Vision -- out of the chaos and drama of Mentor
reabsorbing Calypto back into the mothership, there's a new face to
the C-based synthesis push; a guy named Badru Agarawala who was the
former CEO of Axiom and now the head of MENT Calypto BU. And get
this -- Badru has a "vision" for HLS design! (ESNUG 560 #5) So,
for fun, I want to see if I can meet him at the DAC MENT booth.
Calypto Catapult 10.0 synthesizes SystemC/C/C++ into Verilog/VHDL RTL.
They added HLS coverage for 100% RTL coverage for 2x faster closure.
Synthesizes assertions, generates RTL test pins, removes redundancies,
and integration with Quest CoverCheck. Also made AC_Datatypes public.
NEW! -- Catapult-CPC is their new C++/SystemC formal property checker.
It auto checks array overflow, underflows, uninitialized variables,
divide-by-zero, array bound errors, illegal shifts. Proves user
assertions & cover points. Generates test vectors for reachable code.
Qualcomm, Nvidia, ST, Google, Thales, Ericsson, Fujitsu, Toshiba.
(booth 949) Ask for Badru Agarawala. Freebie: cellphone charger
Cadence Stratus HLS takes in untimed SystemC/C/C++ to generate Verilog
RTL that Design Compiler or CDNS Genus can easily digest. Can do both
control logic and datapaths. Claims better accuracy than Catapult.
This year from hooks into Innovus PnR, Stratus HLS supposedly can see
PnR congestion issues waaay up in your source SystemC/C/C++. (WTF?!?)
Socionext, Samsung, LG, Sony, Realtek, Toshiba, Fujitsu, Ricoh users.
(booth 107) Ask for Brett Cline. Freebie: Denali party tix
Synopsys Synphony C plays here but probably not showing at this DAC.
Calypto SLEC does SystemC/C++/C-to-RTL functional equivalence. Tight
EC with Catapult; less tight vs. SNPS Synphony or CDNS Stratus. Also
C++ assertion/property checks. Now runs "bottom up" to do partitions.
(booth 949) Ask for Thomas Bollaert. Freebie: cellphone charger
Real Intent Ascent Lint works with MathWorks HDL Coder synthesis and
Calypto Catapult synthesis; does hierarchical waiver management. 50
new rules including extensive clock-gating checks and DO-254 ruleset;
25 million lines of RTL/hour; new regression reporting, new database-
driven debug to sort and manage lint analysis.
(booth 527) Ask Lisa Piper. Freebie: a rose
Fraunhofer COSIDE is a system level tool based on SystemC as well
as on SystemC AMS 2.0. Competes vs. Matlab Simulink or MENT Vista.
(booth 1738) Ask for Karsten Einwich. Freebie: cookies
Breker Portable Stimulus gens multi-threaded, multi-processor, multi-
memory C tests for cache coherency and processor-memory workload perf.
Verdi debug. Users Broadcom, IBM, Nvidia, ST Micro, ST-Ericsson.
Cavium used it for 3-chip 144 mixed cores in silicon bring-up lab.
(booth 1626) Ask for Tom Anderson. Freebie: USB cellphone charger
Codasip Studio 6.0 is an ASIP (application processor) dev environment
that generates a C/C++ compiler, debugger, synthesizable RTL and UVM
based verification. AMD, Sigma, CAST. "We love stealing business
from the Synopsys ASIP Designer guys. It seriously annoys them."
(booth 1113) Ask for Neil Hand. Freebie: notepads
Mentor Sourcery CodeBench creates C compilers and embedded C/C++ dev
tools for chips mixing ARM, IA32, MIPS and Power architectures.
(booth 949) Ask for Rami Rachamim. Freebie: USB phone battery
Imperas does virtual platform based software development, debug and
test. Acceleration on multicore hosts. It competes against Cadence
Virtual, Synopsys Virtualizer, Mentor Vista, and Wind River Simics.
NoCs. Fault injection. Linux, FreeRTOS, OpenRTOS, uC/OS, MQX, eCoS.
NEW! -- Imperas OVP has 30 EPKs, 150 CPU models of ARM, MIPS, Altera.
Users are ImgTec, Renesas, Recore, Altera, NIRA Dynamics, AMD, USAF.
(booth 839) Ask for Larry Lapides. Freebie: coasters
BUGHUNTERS
6.) Now that Kathryn Kranen is gone, my first bughunter question at this
DAC is: "what did Lip-bu get after paying $145 million for Jasper?"
Cadence JasperGold has 12 formal Apps now. New this year that
they are showing at DAC'16 are: Unreachability App that finds the
Verilog lines that testing never sees. SEC App which does deep
sequential functional equivalence. ABV-IP App to exhaustively
test IP's compliance to AHB, APB, ATB, AXI3, AXI4, ACE, 5 CHI,
DDR1-3, LPDDR1-3, SDRAM, DFI, OCP. CSR App tests status registers.
Samsung, ST, ADI, Nvidia, Qualcomm, TI, Broadcom, Marvell, Sony.
(booth 107) Ask for Pete Hardee. Freebie: Denali party tickets
Mentor Questa Formal also has Apps for CDC, X-checking, RTL checks,
coverage closure, automatic property generation, connectivity checks,
CSR verification, protocols, plus sequential equivalency checking.
New is PropCheck app and Single Event Upset (SEU) Fault checks.
Formal apps: Secure Check App, Power Aware CDC, Reset Check App.
Users Samsung, Mediatek, AMD, Microsoft, Oracle Labs, HP, Micron.
(booth 949) Ask for Joe Hupcey. Freebie: USB cellphone battery
OneSpin 360-DV does full blown property checking as coverage which
"checks the checks" to direct assertions at uncovered areas. Beats
regular sim stimulus coverage. 360-SystemC does ABV for C++ and
SystemC, now does X-state and race conditions. 360-Quantify does a
full formal coverage of your code and System Verilog Assertions.
NEW! -- 360-Safety injects faults into device code to see if it
recovers from an operational fault in the field, and still works.
Their 360 DV Inspect combines linting with property checking, user
doesn't have to write any assertions! Their 360 EC-FPGA does
equivalency checking RTL vs. post-synthesis netlists for FPGA's.
Renesas, Nokia, Infineon, Xilinx, Western Digital, Bosch, Maxsim.
(booth 1249) Ask for Raik Brinkmann. Freebie: Frisbee thingy
Real Intent Meridian CDC does billion-gate hierarchical verification;
iDebug hierarchical intent analysis and data manager with scope-
based reporting for clock-domain crossing errors. Meridian Physical
CDC has additional glitch and illegal-logic checks for CDC errors in
gate-level netlists. New faster static engines.
(booth 527) Ask Vikas Sachdeva. Freebie: a rose
Synopsys Atrenta Spyglass plays heavily in killer linters, but I
don't know if they got space in the Synopsys booth this year.
Ausdia Timevision-CDC does block/fullchip CDC analysis on RTL or
gates using SDC constraints only -- so it can verify your actual
clock groups as being CDC-safe. Chips of 20 M to 500 M inst with
1000 clocks in 8 hours. GUI user interface with full tracing.
(booth 1119) Ask for Sam Appleton. Freebie: plush armadillo
Excellicon ConDor does CDC claiming "NO setup, fastest run times
on 500M+ insts, flat. Only RTL or netlist input for multi-mode
hierarchical analysis." (booth 1213) Ask Himanshu Bhatnagar.
Blue Pearl Advanced CDC lets engineers visually verify and by way of
graphical FSMs, CDC and false path viewers with cross probing to RTL,
with forward and reverse tracing, and linting message filtering."
Marvell, Microsoft, Harris, Teradyne, Ciena, Xilinx, Samsung, NEC.
(booth 929) Ask for Ellis Smith. Freebie: water bottles
Aldec ALINT does CDC rule checking. Viewer shows violating code.
(booth 619) Ask for Christina Toole. Freebie: plush longhorn steers
Ausdia Timevision also formally verifies design constraints. Does
gate-level and RTL SDC. 20-80M inst, with 1000+ clocks in 8 hours.
Incremental & SDC promotion/demotion. New hierarchical budgets.
New asynchronous clock/data glitch detectors. Maxim, AMCC, Nvidia.
(booth 1119) Ask for Sam Appleton. Freebie: plush armadillo
Excellicon ConCert-ET verifies timing intent & structural exceptions
using SVA+ and formal. ConCert does equiv checking, SDC and CTS
analysis. 500+ M inst. Their ConMan formally compiles hierarchical
constraints for multi/merged mode SDC for synthesis, P&R, STA tools.
It extracts all root and generated clocks, clock groups, exceptions
(FP, MCP), IO's w/ related clock budgeting, and case analysis values.
Promotion/Demotion. Renesas, Qualcomm, Sandisk, Maxim, Microsoft.
NEW! -- ConCert-SI sees if your timing constraints are SI compliant
in order to remove unnecessary pessimism. "Nobody else does this!"
(booth 1213) Ask for Himanshu Bhatnagar. Freebie: swords
FishTail Confirm now verifies if asynchronous resets are safe from
glitches using formal and AVB. Requires no additional input apart
from SDC and RTL/netlist. Runs 5M gate design in 14 min. Confirm
formally proves if IP used to synchronize clock domain crossings is
correct -- no structural checks. Confirm now checks if a merged
constraint file constrains each path in the design the same way as
in the original signoff modes. An MCP that applied to 2M paths on a
10M gate design was formally proven as correct in 20 minutes. All
tools support DC, ICC/ICC2, Innovus, Genus, Nitro-SoC, Atoptech.
Broadcom, TI, Qualcomm, Xilinx, Altera, Cypress, Silicon Labs users.
(booth 1812) Ask for Ajay Daga. Freebie: none
Real Intent Meridian Constraints does SDC generation, validation and
multi-cycle path verification; New functional analysis of MCPs and
constraints exception verification removes need for formal analysis.
Gives 50% faster sign-off. Constraints promotion from block-level
to top-level. New iDebug for database-driven smart reporting.
(booth 527) Ask Vikas Sachdeva. Freebie: a rose
NEW! -- Arcadia Innovation TimeHawk Constraints finds SDC patches
used to be identified during placement and CTS iterations. Saves
3 to 4 weeks of design iterations. It also does full chip SDC debug,
gate-level timing, interface timing, rule checks. It's interactive.
Does 10+ million inst designs that are "run in a couple of minutes."
(booth 1313) Ask for Joey Lin. Freebie: pens
Real Intent Ascent XV does X-propagation checks. Ranks X-sources
and X-sensitive nets by failure importance. Initialization audits.
Setup-free X-pessimism analysis at gate-level with only 3X overhead
versus 5x-10X from other tools. Replaces using VCS/Incisive/Questa's
X-safe simulation switches. Finds the minimally correct reset
schemes; smarter reporting with new iDebug debugger
(booth 527) Ask Lisa Piper. Freebie: a rose
Avery SimXACT automatically find X bugs in RTL and eliminates false
X's in gate-level simulation. Has gated clock X pessimism analysis
and auto generated fix deposits. Verdi App to graphically view
force/release fixes as well as any real X backtrace logic cones.
(booth 800) Ask for Chris Browy. Freebie: USB cellphone battery
Mentor Visualizer Debug is Wally's debug answer to Cadence SimVision
Debug Analyzer and Synopsys DVE/Verdi. Visualizer debugs RTL, gates
and testbenches, automatic tracing to "pinpoint cause of errors".
(booth 949) Ask for Gordon Allan. Freebie: USB cellphone battery
Cadence Indago is Lip-Bu's answer to Aart's Verdi3 empire. Indago
debug works by adding Big Data Capture to Root Cause Analysis -- in
order to data mine your CDNS tool run logs -- to "highlight causality"
and correlations causing your bug in the first place. Indago's big
idea is to data mine in order to do fewer simulation reiterations.
This year at DAC the Indago guys are pitching HW/SW bug hunting now.
(booth 107) Ask Adam Sherer or Larry Melling. Freebie: Denali tix
VERIFICATION IP
7.) Second year MENT VIP surveyed waaaaay on top with users. (DAC'15 #9)
Mentor Questa Verification IP (VIP) is a big ass library of UVM VIP.
- AMBA Family (CHI 5, ACE 4, ACE-Lite, AXI4, AXI3, AHB, APB);
PCIe Family (PCIE 4.0, PCIe 3.0, PCIe 2.0, PCIe 1.1, PIPE, PIE-8,
SR-IOV, MR-IOV, NVMe, AHCI); USB Family (USB 3.1, USB 3.0+OTG,
USB PD, PIPE, xHCI, SSIC, USB 2.0+OTG, UTMI+, UTMI, ULPI, oHCI,
eHCI); Ethernet Family (100G, 50G, 40G, 25G, 10G, 1G, 100M, 10M,
PTP, MDIO, EEE, MII, RMII, GMII, TBI, RTBI, SGMII, RGMII, QSGMII,
BASE-X, BASE-T, BASE-R, BASE-W, CAUI, XGMII, XAUI, XLAUI, RXAUI,
HI-MoM, XSBI, XLGMII, CGMII, HiGig2, FEC, Auto-Neg); Serial Family
(SmartCard, SPI-TI, SPI-Moto, SPI-NS, SPI 4.2, UART, I2C 5.0,
I2S-Philips, I2S-TI, JTAG); MIPI Family (MPHY 3.0, LLI 2.0,
DSI 1.1, CSI-3, CSI-2, DigRFv4 1.2, HSI 1.0.1, Unipro 1.6,
UFS 2.0); DDR Family (LPDDR4, LPDDR3, LPDDR2, DDR4, DDR3, DDR2,
DFI 3.1, Wide IO 2, DRAM Model Generator); HDMI Family
(HDMI 2.0, HDMI 1.4, HDCP 1.4);
- New memory VIP library: DDR 2/3/4, LPDDR 2/3/4, DIMMs, HBM2,
HMC, SDIO, SDCard, eMMC, ONFI, Toggle, UFS and Hyperbus
Each protocol comes with a testplan, functional coverage, assertions,
examples and stimulus. ARM, Cypress, Microsemi, PLDA and ST users.
(booth 989) Ask for Mark Olen. Freebie: USB charger
Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
- have VIP for "AMBA 5 CHI, eMMC 5.0, HDMI 2.0, LPDDR4, MIPI C-PHY,
MIPI CSI-3, MIPI SoundWire, Mobile PCI Express, PCI Express Gen 4,
USB SuperSpeed Inter-Chip, Wide I/O 2" plus new "Ethernet 25G/50G,
HBM, HMC, MIPI DSI-2, WiFi MAC".
Denali-style API, all simulated VIP runs on VCS, Questa and Incisive.
"VCS or Questa customers do not need Specman e". TripleCheck.
Broadcom, HP, IBM, Intel, LSI, Hitachi, Marvell, Qualcomm, Samsung.
(booth 107) Ask Susan Peterson. Freebie: Denali party tix
Avery Verification IP (VIP) for PCIe Gen4, DDR4 LRDIMM/RCD2/DB2 and
3DS, MIPI CSI and DSI for C-PHY/D-PHY, eMMC 5.1, NVMe 1.2, USB 3.1
(Gen2) Superspeed+ and Power Delivery and xHCI 1.1, Unipro 1.6,
Soundwire. Added HBM, Toggle Flash, Automotive CAN, LIN, FlexRay.
"Save $$$! Access all 50 of our VIPs with one portfolio license!"
User Seagate, Samsung, Broadcom, Xilinx, Marvell, SKHynix, SanDisk
(booth 800) Ask for Chris Browy. Freebie: cellphone charger
Oski ACE/CHI Interface and Coherence Formal VIP checks compliance
to those interfaces. Funny story: The Oski ACE/CHI Formal VIP
out-performs Cadence VIP/ProofKits even on the JasperGold tool!
(booth 339) Ask for Vigyan Singhal. Freebie: USB battery
SmartDV VIP claims 90 VIP and 41 sim acceleration IPs. (booth 1641)
MARGINs & ECOs
8.) Dorado Tweaker is a family of physically-aware ECO tools:
Funct. ECO / Timing ECO / Power ECO / Metal ECO / Clock ECO
Tweaker-F1 / Tweaker-T1 / Tweaker-P1 / Tweaker-M1 / Tweaker-C1
Synopsys PrimeTime-ECO vs. Tweaker-T1
Cadence Tempus-ECO vs. Tweaker-F1
Static/dynamic power ECO's. 50 M inst. 16/14/10/7nm FinFET. Now
hierachical/low power/timing/CPU ECO flows. Intel/GF/Samsung/TSMC
Broadcom, Qualcomm, LG, TSMC, Mediatek, Samsung, Altera users.
(booth 1513) Ask for JJ Hsiao. Freebie: wooden toy
ICScape TimingExplorer is a physically-aware MCMM timing ECO tool.
PBA-based timing fixes, route-based timing fix. 16/14/10/7nm It's
2X faster now. ClockExplorer does CTS clock analysis and constraint
generation. Cuts clock insertion delay. Marvel, Hisilicon users.
(booth 738) Ask for Jason Xing. Freebie: car tool kit
Cadence Conformal ECO Designer generates "congestion-aware ECO"
for "last-minute difficult ECO areas". Broadcom, Qualcomm, ST.
(booth 107) Ask Kenneth Chang. Freebie: Denali party tix
Synopsys PrimeTime DMSA is all about distributed MCMM timing ECO's.
(booth 149) Ask for Robert Hoogenstryd. Freebie: pens
PRIMETIME & RIVALS
9.) Synopsys PrimeTime is world's 87% marketshare STA tool. Also does
noise analysis. Chatting up AOCV and DMSA hooks year. Stanford
Unversity, Nvidia, and TSMC talking at PrimeTime SIG on DAC Monday.
(booth 149) Ask for Robert Hoogenstryd. Freebie: pens
Cadence Tempus is Lip-bu's answer to Aart's PrimeTime STA monopoly.
50 M inst design in PrimeTime took 8.5 hours on 8 CPUs; Tempus did it
in 58 min on 32 CPUs. Generates legalized placement directives in MCMM
timing optimization for 20/16/14/10 nm placement rules. "No need for a
placement tool to legalize ECO's, it's a big boy." 100 M insts/hour.
Tempus is "industry's first fully distributed, massively parallel STA
tool" and "can easily 1 billion placed insts". 16/14/10nm certified.
7nm ready. Does STA inside Virtuoso with Quantus QRC. Tempus has
over 200 tapeouts. TI, Qualcomm, Broadcom, ST, NXP, Sharp, LG, ARM.
(booth 107) Ask for Ruben Molina. Freebie: Denali party tix
Arcadia TimeHawk STA is the "first commercial timer to bring AI, as
in artificial intelligence to timing signoff. Reduces pessimism by
countering inherent inaccuracy in STA models to achieve best SPICE
correlation." TimeHawk does ECO advisory, physical-aware, 1+ M inst
per minute, 2 billion capacity, SI, MMMC. Super easy set-up.
(booth 1313) Ask for Joey Lin. Freebie: pens
CLK-DA Variance FX and Path FX plays in this niche but they're not
at this year's DAC for some reason? Ask Isadore Katz?
EMULATION / ACCELERATION / PROTOTYPING
10.) NEW! -- Cadence Palladium Z1 has 22 use models like dynamic power
analysis with Joules, UPF/CPF, full ICE in MHz, Sim acceleration
(RTL & Gates). Its coverage can be merged with coverage from
simulation, virtual & hybrid, system environment virtualization,
60x faster SW bring-up, virtual verification machine for offline
debug. Scales to 9.2B ASIC gates for 2,304 simultaneous users in
emulation data center. 5x better throughput. Real targets can be
reallocated to emulation jobs virtually, up to 30m away. Dynamically
reallocates job to prioritize and decrease job fragmentation for
2.5x better utilization. Nvidia, Huawei and PMC Sierra/MicroSemi
are public Z1 users. Pairs with Cadence Protium for fast bring-up on
FPGA. CDNS ARM System Development Suite is optimized for ARM v7/v8
based chips, HW/SW co-design, debug, interconnects, OS bring-up.
(booth 3515) Ask Frank Schirrmeister. Freebie: Denali party tix
Mentor Veloce 2 does 50+ MHz embedded SW execution with Warpcore and
Codelink. VirtuaLAB peripherals: 256-port Ethernet, PCIe Gen3, USB-3,
SATA, SAS, VJTAG. RTL-waveform debugger. Networking chip guys use
Veloce 2; and storage chip guys eager to use both its ICE and Virtual.
Broadcom, Mitsubishi, NXP, ST, Trident, ZTE, HiSilicon use Veloce 2.
NEW! -- MENT Veloce Apps. Last year their Power App was a super tight
integration with Ansys Apache PowerArtist. It got RTL power reduction
analysis 4.5X faster. Now there are 7 more Apps: Coverage, Assertion,
Deterministic ICE, ICE, Power, SW Debug and DFT -- plus a brand new
Ixia Virtual Network App being secretly demoed at DAC Mentor booth.
(booth 949) Ask Jean-Marie Brunet. Freebie: USB cellphone battery
Synopsys EVE ZeBu-3 claims 4X faster and can do 3 B gates. TLMs,
power-aware, simulation acceleration, ICE, synthesizable testbench.
Claims small footprint, low weight, and very modest power/cooling.
(booth 149) Ask for Tom Borgstrom. Freebie: pen
ProDesign proFPGA is like SNPS HAPS but based in Germany. Mix match
Xilinx Virtex 7 330T to 2000T to Altera Stratix 10. 600 M ASIC gates.
13.1 Gbps. In 3 years ProDesign shipped 751 units to 61 customers.
(booth 2218) Ask for Gunnar Scholl. Freebie: hugs
S2C Prodigy Player Pro 6.3 is like HAPS but from a start-up. Virtex
and Kintex UltraScale. Multi-board partioning. Pin multiplexing up
to 1.6GHz LVDS. Mix quad, dual, single logic modules. Cable set-up
after partition. Supports multi-board standalone & Cloud Cube mode.
(booth 1928) Ask for Richard Chang. Freebie: paid blogger book
Aldec HES-7 now uses UltraScale U440's. Claims 633 M gates. Auto
partitioning, ASIC-to-FPGA clock conversion, static/dynamic probes,
memory viewer, HW breakpoints. Ethernet, USB, USB-OTG, HDMI, I2C,
SPI, RS232, GPIO, ARM Debug & JTAG. Qualcomm, Samsung, Fuji-Xerox.
Their HES-DVM does System Verilog DPI-C TLM's, virtual SW, ICE.
NEW! -- Aldec TySOM Ty-1 is a system-on-module development board of
a Xilinx Zynq XC7Z030, memories (512MB DDR3, uSD), communication
(Ethernet, USB, Pmod, JTAG) and multimedia. Reference designs and
Linux ports. For IoT, ARM, Automotive, UAV/UAS, Home Automation.
(booth 619) Ask for Christina Toole. Freebie: texas longhorn dolls
Dini Group DNVUF4A -- ASIC prototype 4 Virtex UltraScale XCVU440's,
each with capacity of 116 million ASIC gates. Seamless stack 8 or
more of these boards to prototype 1 billion ASIC gates. 2,892 BGA.
16 GbE with no external Phy needed. GEN3 PCIe, SATA III, USB 3.0.
Dini Group DN_ReadBacker lets you read back the complete status
of your FPGA registers for debug. "No one else does this, John!!!"
(booth 2401) Ask for Mike Dini. Freebie: grumpy Mike sayings
Cadence Protium, a homebrew FPGA-based prototyper. Lip-bu's answer
to SNPS HAPS. Auto ASIC-to-FPGA memory conversion, clock tree
transformation, pre-P&R model validation. "quick bring up in 4-6
weeks instead of 3-4 months." SCE-MI based transaction interface.
NXP, Nvidia, Hitachi, Sony, Microsemi, Medtronic, Solarflare.
(booth 107) Ask for Juergen Jaeger. Freebie: Denali party tix
Synopsys HAPS-80 and ProtoCompiler claims 1.6 billion ASIC gates
at 100 Mhz speeds from 64 total Xilinx Virtex UltraScale VU440's.
(booth 149) Ask for Joachim Kunkel. Freebie: pens
PLDA QuickPlay is in this niche, but it's confusing. (booth 643)
SPICE & AMS
11.) MENT BDA AFS was 5x-10x faster vs CDNS Spectre in ESNUG 495 #4 and 2x
faster than SNPS FineSim Pro in ESNUG 535 #3. Now 20+ M elements.
Now TSMC 7nm certified. BDA ACE fully replaces Virtuoso ADE-XL for
analog characterization runs. AFS Mega does SPICE of 100+ M element
mega arrays like memories. It does DC, transient, transient with
dynamic temp, alters, sweeps, Monte Carlo. TSMC uses AFS Mega for
all 10nm SRAMs. Samsung, MediaTek, Intel, Broadcom, Qualcomm users.
Something is going on at the MENT BDA group. I'm hearing that some
key veteran EDA sales/marketing/AE's are defecting over to them.
(booth 949) Ask for Giuseppe Oliva. Freebie: USB cellphone charger
NEW! -- Silvaco SmartSpice Pro is Iliya's new push into the memory
fastSPICE market. Claims "true SPICE behavior but with much faster
generation of waveforms" and "2X speed-up on AMOLED panel and SRAM
designs with better waveform overlay results than other simulators."
Does 28/16/14/10nm. SmartSpice (golden), SmartSpice HPP (parallel).
(booth 649) Ask for Colin Shaw. Freebie: tin cups & golf balls
CDNS Spectre-XPS is Lip-bu's comeback FastSPICE tool for memories.
Benchmarked 3-4X faster throughput than SNPS HSPICE in ESNUG 547 #3.
Has clever fast-or-accurate partitioning based on need. Multi-core.
(booth 107) Ask for Wilbur Luo. Freebie: Denali party tickets
ProPlus NanoSpice Giga big ass capacity parallel SPICE. Did 576 M
element full-chip DRAM, 50.5 M transistor SRAM and 67 M element post-
layout SRAM. Does 1+ B elements for 16/14/10/7nm FinFET or 28nm
FD-SOI. 10X faster vs. parallel SPICE. Dolphin and Attopsemi users.
(booth 1219) Ask for Lianfeng Yang. Freebie: cell phone clip
NEW! -- ProPlus ME-Pro lets you benchmark fab processes and devices.
Compare multiple foundries/multi-processes down to 7nm. No scripts
nor SPICE licenses needed to do 100's of comparisons! Qualcomm
(booth 1219) Ask for Lianfeng Yang. Freebie: cell phone clip
EdXact Jivaro does netlist reduction for SPICE sim acceleration.
Their Viso does circuit design analysis. Now tighter with Virtuoso.
New resistanceMap, voltageMap, delayMap, selective DC-path analysis.
(booth 1722) Ask for Mathias Silvant. Freebie: pens
Solido Variation Designer does variation-aware design for PVT corners,
3 to 7-sigma Monte Carlo, hierarchical and sensitivity. Big thing
is it cuts waaaaaaay down on how many SPICE runs you need. Demoing
new 4.0 release with new GUI and CLI for memory, std cell, analog/RF,
custom digital. TSMC, Broadcom, Nvidia, Huawei, Cypress, ARM, IBM
(booth 611) Ask for Amit Gupta. Freebie: VR Demo
MunEDA WiCkeD analyzes SRAM cell/column/array, std cell, and analog
circuits for local variation to 9-sigma. Hierarchical and WCA.
FinFET, Bulk, Bipolar, BiCMOS. ST Micro and MunEDA published
silicon & bit cell analysis of 14nm FDSOI statistical BTI effects.
Samsung, SK Hynix, Infineon, Sanyo, Toshiba, and Altera users.
(booth 1438) Ask for Andreas Ripp. Freebie: tote bags
ProPlus NanoYield is variation analysis on yield vs. PPA trade-off.
It does High Sigma Monte Carlo. Licensed from IBM eight years ago.
Can handle 10,000+ variables and does up to 7-sigma. Used by SMIC.
(booth 1219) Ask for Lianfeng Yang. Freebie: cell phone clip
Silvaco Variation Manager is the old Infiniscale IClys which does
Monte Carlo to 50X, and High-Sigma analysis 1,000,000X to 8 sigma.
Supports non-Gaussian. Batch mode library verification, too. They
also have Library Variation Manager that does characteration of 100's
of cells for you. For example, 28nm FDSOI, 40 cells, 100 corners,
Monte Carlo at each corner, 100's of measures, took 173 mins using
brute force MC and only 19 mins on Library Variation Manager.
Both ST Microelectronics and Dolphin Integration uses Silvaco tools.
(booth 649) Ask for Firas Mohamed. Freebie: tin cups & golf balls
Cadence Virtuoso Liberate LV/MX/Variety is rename of Altos cell lib
characterizer. Does electrical cell views for timing (NLDM), power
(NLPM) and signal integrity. CCS, ECSM, CCSN, ECSMN, AOCV/SOCV/LVF.
Likes Spectre APS. Rivals Liberty NCX, SiliconSmart, Mentor Kronos.
(booth 107) Ask for Ahmed Elzeftawi. Freebie: Denali party tix
Integrand EMX is a 3D EM simulator for modeling on-chip passives and
interconnect and RF. Black boxing models active circuitry. Now
simulating full VCOs. Samsung, Broadcom, Nvida, MediaTek, TSMC, UMC.
(booth 320) Ask for Sharad Kapur. Freebie: stress doll
Helic Exalto does fast electro-magnetic inductance aware modeling of
on-chip interconnect and passives. Allows designers to put large
passive devices over active circuitry or decoupling capacitors.
Fast - 3 LC tank VCO in 55 sec. High-Capacity - 2mmx300u 3 metal
clock network shielded with power mesh modeled (w/ full coupling) in
118 min on 16GB RAM machine - no layout simplifications required.
Rivals are HFSS, Momentum. Users are Qualcomm, Huawei, NXP, Altera.
(booth 819) Ask for Yorgos Katsoulis. Freebie: squeeze baseball
IROC Tech TFIT predicts soft error FIT rate on CMOS digital cells
from SPICE netlist, GDS2, foundry models. TSMC, GF, Samsung, ARM.
(booth 1638) Ask for Olivier Lauzeral. Freebie: USB flash drive
DESIGN COMPILER & RIVALS
12.) Mentor Oasys-RTL does crazy fast RTL synthesis, floorplanning, and
design partitioning. Took 3 hours to synth and floorplan a 2 M inst
chip. Can do 6 M inst flat. (ESNUG 560 #6) MENT selling it as a
standalone RTL synthesis tool to take on Design Compiler. Intel,
TI, Broadcom, Juniper, Qualcomm used Oasys. Xilinx Vivado is Oasys.
(booth 949) Ask for Sudhakar Jilla. Freebie: USB cellphone charger
Cadence Genus is the newest attack on Aart's 30 year Design Compiler
franchise. It's Anirudh's home-grown, massively parallel RTL and
physical synthesis tool that's "5X faster" than Design Compiler,
"1/2 iterations between unit and block/chip-level synthesis", and
has "timing/wire lengths with 5% of Innovus PnR", and has "20% less
datapath area!". Texas Instruments and ImgTec are Genus users.
(booth 107) Ask for David Stratman. Freebie: Denali party tix
Synopsys demoing both Design Compiler Graphical and DC Ultra Topo.
"Physical guidance to IC Compiler tightens correlation of timing,
area, and power to within 5% and speeds placement by 1.5X." Also
claims "10% smaller area plus reduced congestion and leakage."
(booth 149) Ask for Gal Hasson. Freebie: pens
BIG DATA & ANALYTICS
13.) IC Manage Envision is a tapeout predictor based on Big Data. It was
last year's #1 tool. After data mining 2 years of company-wide 28nm
man-hours and 28nm EDA tool run logs, Xilinx used Envision to predict
their Zynq 20nm migration tapeout to within +/- 1 week. ESNUG 550 #1.
New this year at DAC is they've added customizable dashboards.
(booth 1329) Ask for Shiv Sikand. Freebie: candy
Consensia PinPoint is web based analytics on every aspect of
ASIC/FPGA design from synthesis, CDC, STA, CTS, power to layout, so
design teams get to design closure faster. Qualcomm, Avago users.
Is this the old Tuscany PinPoint that Dassault bought 4 years ago?
(booth 2219) Ask for Dave Noble. Freebie: stress ball
RTL & GATE POWER
14.) Calypto PowerPro does RTL power optimization. Users see 9% to 12%
general Verilog RTL power savings. 37% cut in sequential logic power
saving in ESNUG 535 #2. Chatting up their "What If" ability with
to quickly understand power effects of potential mode, operating
environment or design changes "saving hours of turn-around-time".
PowerPro is only tool that's tight with Calypto SLEC-Pro sequential
EC. Verifies low power RTL tweaks are equivalent to original RTL.
UPF and SPEF. Physically-aware. Models clock tree, multi-Vth libs,
SPEF extraction of WLM. Has ~85% correlation against gate-level.
16/14nm FinFET. Samsung, ARM, HiSilicon, Google, Freescale users.
(booth 949) Ask for Thomas Bollaert. Freebie: 2800 mAh charger
Apache PowerArtist users saw 3% to 10% reductions. Does automatic
and guided. Sequential and combinational clock-gating constructs,
memory light/deep sleep modes, and wasted power in datapath logic.
RTL power accuracy within 10% of sign-off. 10 M gates in an hour.
16/14/10/7nm. Handles 100M+ instances. Hooks with RedHawk for
power grid integrity. Also peak power & thermal hotspot analysis.
Has tight hooks into MENT Veloce emulation and Power App. Activity
streaming 10X faster vs. old slow FSDB for millisecs of activity.
Users are Broadcom, Nvidia, Samsung, ST, NXP, Toshiba, ARM, Ciena.
(booth 1449) Ask for Preeti Gupta. Freebie: stuffed dog
Synopsys Atrenta Spyglass Power users got 9% to 16% power cut on
Verilog RTL. RTL, gate-level, or post-layout. FSDB, VCD, SAIF
and vectorless. Does ECO's, CPF, UPF, mem in sleep mode. ERC
checks on P/G netlist. Power modeling and coarse clock gating.
(booth 149) Ask for Piyush Sancheti. Freebie: pens
NEW! -- Cadence Joules is an RTL power calculator. Estimates power
at RTL to 15% of signoff power, time-based power up to 20X faster;
(booth 107) Ask Krishna Balachandran. Freebie: Denali party tix
CDNS JasperGold Low Power App formally verifies lower power designs
that have multiple voltage and power-management domains. Checks to
see any issues the after the insertion of power management circuitry.
(booth 107) Ask Pete Hardee. Freebie: Denali party tickets
Cadence Sigrity does chip/package/board signal and power integrity.
Just like what Ansys/Apache Sentinel does. Lattice uses Sigrity.
(booth 107) Ask Brad Griffin. Freebie: Denali party tickets
LibTech ChipTimer does post-synthesis, pre-layout timing, area, power
optimization, and post-layout leakage power opto. Layout aware. 20%
to 2X less. "But we cut leakage power by 4X on a customer's 1.2M gate
16nm design using same library and no change in critical path timing."
(booth 743) Ask for Mehmet Cirit. Freebie: none
Cadence Conformal Low Power does EC "from RTL to transistor level."
It natively supports IEEE 1801. Qualcomm, Broadcom, Marvell, ARM.
(booth 107) Ask Kenneth Chang. Freebie: Denali party tickets
CALIBRE, STAR-RC, & RIVALS
15.) Calibre Pattern Matching replaces text-based design rules with visual
geometry capture and compare. A visual approach significantly cuts
rule deck size and complexity. It completes against Cadence Pattern
Analysis, Synopsys IC Validator, Anchor D2DB-PM. It kicks ass on
regular SRAM elements, and for curved structures like analog, RF, and
MEMS. Now has Auto-Waivers for visual DRC checks to save time. Also
quickly locates & removes design patterns that are "yield detractors".
Aimed at 10/7nm designs. Samsung, eSilicon, GlobalFoundries, SMIC.
(booth 949) Ask for Jonathan Muirhead. Freebie: cellphone charger
Calibre nmDRC does 10 B devices full reticle 10nm designs in 9.6 hours
overnight. Triple patterning, Self-Aligned Double Patterning (SADP),
hot spot pattern matching detection, voltage aware spacing. It's the
Golden 10nm DRC/LVS sign-off at Samsung, TSMC, GlobalFoundries, UMC.
(booth 949) Ask for John Ferguson. Freebie: cellphone charger
Calibre RealTime lets engineers do instantaneous sign-off DRC checks
during digital PnR inside ICC/ICC2, Innovus, Nitro-SoC, Atoptech.
"Same deck, same results as batch Calibre." Double/triple patterning,
pattern matching, voltage-aware DRC, density checks. 16/14/10/7nm.
(booth 949) Ask for Srinivas Velivala. Freebie: cellphone charger
Virtuoso IPVS is on-the-fly signoff DRC checks as you custom design.
It does DPT odd loop detection with fixing hints for designers in
16/14/10/7nm FinFET/FD-SOI flows. Annotation Browser cross probing.
Renesas, Cortina, ST uses IPVS. Only instantaneous DRC in Virtuoso.
NEW! -- Cadence Innovus-PVS does signoff DRC/LVS, Programmable ERC
(PERC), full metal fill integrated in Innovus, DFM fill, full multi-
patterning color decompositions. Tight integration with Virtuoso
(IPVS). Certified at TSMC/GlobalFoundries/UMC/Intel 64nm to 7nm.
Innovus-PVS track based fill used in production at 16/14/10nm!
Claims to have 5-10x faster ECO fill, 4-5x faster full chip fill.
(booth 107) Ask for Manoj Chacko. Freebie: Denali party tix
Cadence Quantus QRC competes with Star-RCXT and Calibre-xACT. Does
multi-corner/statistical/inductance RLCK extraction, 16/14/10/7nm
Modeling, distributed processing, netlist reduction, SNA. Double
patterning, 3D-IC. 41 FinFET customers and 3 FD-SOI. Reliability.
Constraint validation. Works "in-design" in Innovus and Virtuoso.
(booth 107) Ask for Hitendra Divecha. Freebie: Denali party tix
Mentor Calibre-xACT does massively parallel full chip RLC parasitic
extraction without tiling. Processes entire net on a dedicated CPU.
No boundary and halo effects. "Attofarad accuracy with multi-million
instance digital or custom designs." 3D field solver. Cypress user.
(booth 949) Ask for Christopher Clee. Freebie: cellphone charger
EdXact Belledonne compares layout versus layout, quickly finds the
differences with respect to wiring, and tells if diff is important.
(booth 1722) Ask for Mathias Silvant. Freebie: pens
Sage iDRM is a physical design rule compiler. It finds all places
in your physical design where your "test" rule applies -- plus where
it's been violated. It helps make sensible DRC decks. 22nm - 7nm.
(booth 421) Ask for Coby Zelnik. Freebie: pens
Coventor SEMulator3D is a tool for the fabs themselves to simulate
the manufacturing process in 3-D. Virtual fabrication. Test fab
effects early. New resistance and capacitance extraction this year.
New analysis editor, too. GlobalFoundries, Micron, IBM, Imec users.
(booth 321) Ask for David Fried. Freebie: none
RTL ENVIRONMENTS/SIMULATORS/TOOLS
16.) Synopsys Verdi3 is the wildly popular design debug waveform viewer
with a Qt-based GUI. Aart got it with SpringSoft. Man, it does
everything! UVM, OVM, System Verilog, VHDL, SVTB, VMM, SVA, CDC,
FSBD, UPF/CPF, nWave, nSchema and TFV, PDML, CTS, SDC, STA, HW/SW.
(booth 149) Ask for Thomas Li. Freebie: pens
Verifyter PinDown auto debugs regression failures by IDing the
commits that cause the test failures and automatically assigns bug
reports to the engineers who made these commits. Broadcom uses it.
(booth 1820) Ask for Christian Graber. Freebie: candy
Defacto Star Design tools is an 8-part unified RTL design flow where
coherency between Verilog/VHDL RTL, SDC, IP-XACT, UPF, and SystemC
is guaranteed. Builder does RTL design editing and exploration.
Checker does simulation-free connectivity checks. Low Power does
UPF design exploration. Other parts do padring, DFT, IP, etc. See
review in ESNUG 530 #2. Users Qualcomm, Broadcom, Intel, Maxim-IC.
(booth 1129) Ask for Chouki Aktouf. Freebie: candy
MENT Questa Platform bundles all Mentor Verilog/VHDL RTL simulation,
emulation, low power, VIP, traffic generators, interconnect test,
intelligent testbench, coverage, UVM, formal in one big smudgy bundle.
(booth 949) Ask for Tom Fitzpatrick. Freebie: USB phone battery
SNPS Verification Continuum bundles all the Synopsys simulation stuff
yada, yada, yada... exactly like the MENT and CDNS marketing does...
(booth 149) Ask for Manoj Gandhi. Freebie: pens
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
The Plot Viewer does simple/polar/vector graph and image/color map.
Python support using Cocotb GPI. This enables terse, readable,
maintainable code while providing easy Python abstraction to RTL.
(booth 619) Ask for Christina Toole. Freebie: plush longhorn steers
Amiq DVT Debugger Add-On is an add-on to VCS/Questa/Incisive to let
an engineer NOT have to continuously switch between his editor and the
"e"/SystemVerilog/VHDL simulator. IDE is sorta Visual C like stuff.
Cavium, Cisco users. Specador auto generates HTML documentation.
Their new Verissimo does SystemVerilog testbench code linting.
(booth 1419) Ask for Cristian Amitroaie. Freebie: pens
Agnisys DVinsight is a friendly editor for UVM developement sort of
like Amiq. Helps your write code. And their IDesignSpec converts
specifications for registers/sequences into UVM/RTL. NASA, Intrinsix,
HGST, Icron, Conexant, Wipro, Conexant, John Deere, CERN uses Agnisys.
(booth 420) Ask for Anupam Bakshi. Freebie: beer bottle opener
HARD & SOFT IP
17.) ARM showing new Cortex A-73 CPU, Mail G71 GPU plus its 32/64-bit
RISC CPU's, memory IPs, Artisan std cell libs, plus ARM Socrates
for IP configuration & SoC assembly, plus ARM Coresight/CoreLink
(booth 1748) Ask for Brenda Wescott. Freebie: tiny vodka
Synopsys showing new DW EV61 embedded vision processor. 800 MACs
per cycle. 4K. Also sell Virage DW ARC 600 & 700 cores, plus
mem IP, plus std cell libs; that all directly compete against ARM.
ARC now has 171 customers. DW ARC comes in low power and audio.
(booth 149) Ask for Mike Thompson. Freebie: pens
Cadence IP Portfolio has interface IP for USB, PCIe, MIPI, Ethernet;
analog mixed-signal IP for SerDes, ADC, DAC, AFE, power management;
peripheral IP for I2C, I2S, PWM; Denali memory IP for DDR, LPDDR,
WideI/O, NAND Flash; Tensilica for baseband, audio, imaging/video.
(booth 107) Ask for Pieter Vorenkamp. Freebie: Denali party tix
NEW! -- Silvaco Chip DNA Analyzer scans chip-level database and lists
all detected IP and versions of that IP. Works for embedded SW, too.
DAC IP TALK: "I didn't mean to steal your IP... and other tales"
(booth 649) Ask for Warren Savage. Freebie: tin cups & golf balls
NanGate IoT Std Cell Libs are "IoT optimized" full custom libraries.
9000 cells, 5 VTs, 3 gate lengths. 28/40/65/90nm silicon proven. Cut
area by 8-14%. "Our 8T 28nm GF lib got 55% higher raw gate density."
(booth 442) Ask for Jens Michelsen. Freebie: pens
Cadence TenSilica Fusion DSP is for IoT. New low energy benchmark.
16-bit quad MAC, FPU, AES encryption, standard options, acceleration.
(memory types and structure, I/Os, interfaces) plus ARM or MIPS CPUs.
Used in Epson GPS watches, Toshiba IoT uP, Megachips IoT sensor hubs.
(booth 107) Ask for Chris Rowen. Freebie: Denali party tix
Codasip Codix IP competes vs. TenSilica and ARC. 16-bit cacheless
DSP, 32-bit RISC, 6-stage 32-bit VLIW. "M0 class design but with
2X performance & smaller code size; 10X better w/ customer tweaks."
(booth 1113) Ask for Neil Hand. Freebie: pens and notepads
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precision clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 644) Ask for Mahesh Tirupattur. Freebie: none
CAST has a mess of 8051 cores, GPU and accelerator IP cores, CAN FD,
H.264 Video encoders, JPEG IP. (booth 541) Ask Nikos Zervas.
EnSilica Ltd. sells configurable 16/32-bit eSi-RISC, eSi-Crypto,
eSi-Comms, eSi-Connect. (booth 1742) Ask for Ian Lankshear.
Omni Design sells ADCs, DACs, bandgaps, oscillators, LDOs, temp
sensors. 28nm to 180nm. For IoT. (booth 2018) Ask Denis Daly
PLDA sells IP for SuperSpeed USB, PCI Express, PCI-X, 10Gb TCPIP
for ASICs and FPGAs. (booth 643) Ask for Jean-Yves Brenna.
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". (booth 1539) Ask for Micke Wersall
.
SiLab Tech sells USB 3.1 PHY, Serdes, MIPI, high speed ADC & DAC,
low jitter PLLs. (booth 1442) Ask for Yossi Yehiel.
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180nm to 16FF+. (booth 827) As for John Maneatis.
TEST/SCAN/BIST/JTAG/FAULTS
18.) Here's why Wally's test brainiacs beat out Aart in ATPG/scan test.
Mentor TestKompress does hierarchical ATPG. Patterns are generated
independently for each core. Can be retargeted at chip top-level.
10x faster generate time and 1/10th CPU time of Synopsys TetraMAX.
Pattern count is 1/2, so less test time. Also this core-level ATPG
means no wait for whole design to be done before ATPG generation.
TestKompress IP can be integrated during the RTL design phase, means
DFT isn't pre-tapeout problem. ICC/ICC2, Innovus, Nitro-SoC, ATOP.
Users are Broadcom, NXP, Renesas, On Semi, Intel, NXP, Mediatek.
Mentor Tessent ScanPro places test points in netlist for compression.
Adding 1%-2% area for a 3X to 4X reduction in ATPG test patterns.
If 100X compression with TestKompress, ScanPro gets 300X to 400X.
Mentor Tessent LogicBIST with TestKompress is both manufacturing
and in-system test. Random and deterministic compressed patterns
minimize manufacturing test times by another 2X. Random alone can
do ISO 26262. Random invoked Power-On or functional operation.
Mentor MemoryBIST does at-speed testing, diagnosis, repair, and
debug of embedded memories. Hierarchical, allowing BIST and
self-repair on individual cores as well as at the top level. Ups
yield signifcantly. Wally's reply to Aart's STAR Memory System 5.
(booth 989) Ask for Steve Pateras. Freebie: USB phone charger
NEW! -- Cadence Modus Test does scan insertion, compression, ATPG,
logic and memory BIST. Physically aware 2D elastic compression
that cuts test logic wirelength by 2.6X. Compression ratios of
400X. Takes 1/3rd tester time. Works with CDNS Genus RTL synth.
PMBIST. Soft programmable test for FinFET SRAMs and automotive.
Texas Instruments, GlobalFoundries, Microsemi, Sequans users.
(booth 107) Ask for Rod Metcalfe. Freebie: Denali party tix
NEW! -- Mentor SiliconInsight ATPG used to be memory/logic BIST
diagnosis through a JTAG port. Now uses $100 USB port to access
64 pins. See which scan cells failed or co-ordinates of defects.
(booth 989) Ask for Geir Eide. Freebie: USB charger
Synopsys SpyGlass DFT does "RTL analysis for stuck-at/at-speed
testablity, low power design, JTAG/IEEE1500" and "RTL fault coverage
estimation for stuck-at, transition and random-resistive faults."
(booth 149) Ask Kiran Vittal. Freebie: pens
Synopsys WinterLogic Z01X Safety does fault injection and simulation
(DC, AC, transient faults) for ISO 26262 and IEC 61508 compliance.
Works with SNPS Certitude and rivals CDNS Verifault-XL. User Denso.
(booth 149) Ask for Jason Campbell. Freebie: pens
FPGA STUFF
19.) Mentor Certus does silicon debug for FPGAs, FPGA Prototypes and ASICs.
It rivals Xilinx ChipScope, Altera SignalTap, Synopsys Identify.
"Traced 500 AXI bus signals of a Linux boot sequence (180 seconds)"
(booth 989) Ask for Michael Sachtjen. Freebie: USB charger
Menta eFPGA IP v4 is a unique tool that lets ASIC/SoC designers create
their own TSMC 28HPM or GF 14LPP embedded custom FPGA IP blocks.
(booth 640) Ask for Yoan Dupret. Freebie: honey candy
OneSpin 360 EC-FPGA does equivalency checking RTL vs. post-synthesis
netlists for FPGA's. (booth 1249) Ask for Raik Brinkmann.
ROLL-YOUR-OWN EDA SOFTWARE STUFF
20.) Verific sells System Verilog and VHDL parsers with C++ interfaces to
EDA developers. Perl interface. Parsers for UPF 2.1, PSL, EDIF.
Python APIs. Synopsys, Atrenta, Xilinx, Altera, AMD, Infineon users.
(booth 538) Ask for Michiel Ligthart. Freebie: stuffed giraffe
OneSpin 360-DV LaunchPad lets companies with no formal tools develop
and deliver formal-based apps inside their own in-house EDA SW.
(booth 1249) Ask for Raik Brinkmann. Freebie: Frisbee thingy
WORKSPACE, DESIGN DATA MANAGMENT, & IP TOOLS
21.) NEW! -- IC Manage PeerCache is a Napster style peer-to-peer file
transfer and copy accelerator that enables massively parallel
workflows for source and generated project data. Allows 10+ TB
project data copies and drastically cuts storage. (ESNUG 561 #2)
IC Manage GDP does data management for digital and custom designers
to find, modify, release and track design data through to tapeout.
Samsung, Altera, AMD, Maxim, Nvidia, Broadcom, CSR, Finisar
(booth 1329) Ask for Alex Tumanov. Freebie: candy
ClioSoft SOS does HW configuration management and rev control for
Virtuoso, Laker, Pyxis, Custom Compiler, Keysight ADS. Built-in IP
management and reuse. Does soft integrations with in-house flows.
Huawei, Google, Analog Devices, Infineon, Toshiba, Marvell, CERN
(booth 519) Ask for Karim Khalfan. Freebie: picnic blanket
IC Manage GDP IP Pro maximizes your internal IP reuse -- it can be
a mix of homebrew and purchased IP. Trace bug dependencies. Fixes
across all IP revs and designs. Bug history viewable. Checklist
driven design, testbench reuse. Broadcom, Nordic Semi, Samsung
(booth 1329) Ask for Anthony Galdes. Freebie: candy
ClioSoft SOS IP is where designers can create and upload IPs,
browse, search and compare available IPs, easily track the IP lineage,
issues, defects and their resolutions. New web-style GUI this year.
(booth 519) Ask for Karim Khalfan. Freebie: picnic blanket
NEW! -- Runtime WorkloadXelerator is hierarchical enterprise job
distributed computing environments. It removes the scheduler as a
bottleneck to compute resources, allowing compute farms to be scaled
up without re-architecting the data center. +10 M jobs per day.
Useful for verification regression testing or massive SPICE runs.
(booth 1728) Ask for Stuart Taylor. Freebie: sunglasses
Anyway, I hope this helps! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
|
|
