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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2024"
_] [_
by John Cooley of DeepChip.com
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
EDITOR'S TWO NOTES:
1. if you're an EDA vendor and I messed up somewhere -- please contact me ASAP.
2. the DAC'24 Troublemaker's Panel is at 3:00 in the DAC Pavillion.
My unofficial guide to the San Francisco DAC'24 exhibit floor. Enjoy! - John
NEW SCHOOL RTL SIMULATORS
1.) Metrics DSim Cloud Simulator -- when Joe Costello told me his Metrics DSim was on
par with Xcelium/VCS/Questa, I was skeptical. So, I asked a buddy who has access
to currect revs of those Verilog simulators to benchmark Metrics DSim against them:
open source Metrics Cadence Synopsys Siemens
design DSim Xcelium VCS Questa
--------- ------- -------- -------- --------
Ethmac 0:40 sec 0:14 sec 0:51 sec 0:29 sec
Pci 1:17 0:39 0:57 0:48
vga_lcd 5:52 3:39 6:00 6:12
Notice how DSim's runtimes are on par with VCS and Questa, and it's only 1/2 speed
of Xcelium -- that is, DSim is comparable to a Big Three EDA simulator.
Why this is #1 on my Must See List this year is that Metrics is handing out their
desktop DSim simulator for free. Yup, instead of shelling out $20K to $30K for a
single license for a year -- like with CDNS/SNPS/SIEM -- you can download & run DSim
on your on-prem machine at no cost. No hidden gotchas, no expiration dates. And
it's not limited by # of lines of Verilog, nor gate count, nor your machine size.
You only pay if/when you decide to run DSim in the cloud for extra oomph. It's push
button and costs only 1.5 cents/minute/server. The numbers: running DSim 24/7/365
in the cloud for a whole year sets you back only $7,884. But the BIG payoff is when
you want to use the cloud run your regressions FAST.
Plus, because of distributed jobs "cloud magic" -- running 1 Verilog simulation on
DSim on 1 Azure server for 10 hours costs the same as 100 Azure server for 1 hour.
1.5 cents X 1 server X 10 hours == 1.5 cents X 100 servers X 1 hour == $90.00
But the real benchmark: my same user buddy who ran the original benchmarks tested
this out. He gets even faster (~80X) runtime speed-up in the Azure cloud because
of, again, that distributed jobs "cloud magic":
wall clock time DSim cost
--------------- ---------
1,500 test cases on 1 on-prem server 10 hours free
1,500 test cases in the cloud 7 minutes $8.90
He'd have to pay $$$$ millions for 1,500 licenses to do this with the Big 3 vendors.
I asked Joe: "But why free??". His answer: "Metrics is flipping the EDA business
model on its head. No more choking on license fees. Making a license free removes
our barrier to entry. No purchase orders, no red tape. For chip designers at
small to mid-sized companies, FPGA designers, and students, my free DSim is an
immediate gift for their daily HDL coding, debugging, and small designs. Everyone
can try it, love it -- and then get hooked on the cloud's unlimited fast and cheap
compute power -- free from the usual Big 3 EDA license stranglehold."
"Bottom line, using my DSim saves everyone a ton of time and money," added Joe.
(booth 2548) Ask for Joe Costello. Freebie: a free Verilog simulator
---- ---- ---- ---- ---- ---- ---- ---- ----
Cadence Xcelium (Rocketick RocketSim) is parallelized System Verilog across 100's
of Intel CPUs. In 2016, it benched 23X faster vs. VCS, Questa. (Now it's roughly
only 1.3X to 1.7X faster than SNPS VCS.) It does both gate and RTL sims like VCS.
Xcelium compiles 1 billion gates in 2 hours. Got #3 User's Best of back in 2016,
but that was 8 years ago. Now mildly (30% to 70%) ahead of Sassine's SNPS VCS.
Runs in AWS/Azure/GPC cloud. Xcelium comes in 1K cloud packs at a discount. Runs
SystemC, e/Specman, VHDL, low power. Xcelium Apps like SimAI for machine learning
for coverage closure and bug hunting; X-pessimism for gate level bring up;
Power Playback for parallelization of glitch accurate power estimation. Users
are Intel, Nvidia, Renesas, Samsung, MediaTek, Alif, AutoChips, RealTek, ST, ARM.
(booth 1511) Ask for Pete Hardee. Freebie: lotto stamp
Synopsys VCS with VSO.ai does "shift-left, and is AI-driven" to examine your RTL and
"infer coverage while highlighting areas where coverage is needed" and "high ROI
tests are run first". Says users see "2-10x better regression TAT and functional
coverage up by 5-10%". New this year, multi-die sims and "taint propagation (T-Prop)
for security verification". Intel, AMD, Qualcomm, Broadcom, Nvidia, MediaTek, ST.
(booth 2441) Ask for Bradley Geden. Freebie: pens & coffee
Siemens QuestaSim bundles all Siemens Verilog/VHDL RTL simulation, emulation, low
power, VIP, traffic generators, interconnect test, intelligent testbench, coverage,
UVM, formal in one big smudgy bundle. It has a Profiler for in-depth knowledge of
the design structure for optimal runtime performance. QuestaSim now ships with
Visualizer debug. ISO 26262 certification, real number modeling, P1735 encryption.
(booth 2521) Ask for Mark Olen. Freebee: espresso & beer
BUGHUNTERS
2.) NEW! -- Real Intent Sentry is a totally new static (rules based) signoff tool for
hardware security. It looks for "holes" in your design where malicious code could
sneak in, be executed, and do bad things. Sentry rivals the full formal tools
like the CDNS Jasper Security Path App and SNPS VC Formal FSV and DPV.
The Big-Bang-For-The-Buck here is the runtime and expertise differences between
these 3 tools. The full formal tools from CDNS & SNPS need 12 months to formally
evaluate 100 million gates with a Herr Doctor Formal PhD at the customer driving
it to correctly "mathematically prove" your design with 100% accuracy.
In contrast, Real Intent Sentry's static analysis of 100 million gates is 5 hours;
but static analysis is noisy with false positives -- so it'll take an added 3 weeks
of a regular engineer doing reviews and waivers.
So 3 weeks + 1 normal engineer vs. 12 months + Dr. Formal's time? 3 weeks wins!
I asked Prakash why can't Cadence and Synopsys just have their own RnD create their
own static analysis tools. "It took us 15 years to develop our level of static
analysis expertise; I don't think they [CDNS/SNPS] could duplicate it easily."
(booth 2526) Ask for Pratik Mahajan. Freebie: LED pens
---- ---- ---- ---- ---- ---- ---- ---- ----
NEW! -- Amida Achilles uses "its patented methodology to analyze RTL to reveal
vulnerabilities that formal methods do not cover" and "gives insights into malicious
functional, operational, and data integrity exposures, and how to prevent them."
Huh? Kind of vague. Says it competes against Real Intent Sentry and Cycuity Radix.
Joe Costello is a board member, and Jim Hogan was a founding board member. (It was
built with U.S. Department of Navy funding, so it's from a security mindset.)
(booth 2442) Ask for Margaret Schmitt. Freebie: stuffed eagles
---- ---- ---- ---- ---- ---- ---- ---- ----
Cadence Jasper now has 17 formal Apps. Last year they added:
- Jasper C2RTL app for checking C++ algorithms vs RTL implementation
- Jasper FPV/SEC/Coverage to verify processor- and domain-specific
computing-based designs (including RISC-V)
- Jasper Superlint/CDC/RDC for RTL designers to hand off clean RTL
for further implementation and verification
"Our new artificial intelligence kicks ass!" Jasper Apps finds bugs 1000's of cycles
deep. Tight with Xcelium and Verisium. Tons of users gushed about the JasperGold
Apps years ago. (DAC'16 #1, DAC'17 #11, DAC'18 #7). Google, Intel, ARM, Nvidia,
Qualcomm, Samsung, ST, Analog Devices, NXP, RealTek, MediaTek all use Jasper Apps.
(booth 1511) Ask for Pete Hardee. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
Synopsys VC Formal uses formal techniques to prove a design's correctness. Like
its rivals CDNS Jasper and MENT Questa Formal, it has formal apps (12 apps actually)
like DPV with HECTOR for datapaths (ALU, FPU, DSP etc.), AEP to extract properties,
FCA for coverage analysis, FXP for X-propagation, CC for connectivity, FRV for
register checks, SEQ for sequential checks, FPV for formal properties, FLP of low
power, FSV for security, FuSa for functional saftey, and FTA for testbench analysis.
(booth 2441) Ask for Bradley Geden. Freebie: pens & coffee
---- ---- ---- ---- ---- ---- ---- ---- ----
Siemens OneSpin does niches that Cadence Jasper and Synopsys VC Formal doesn't
do -- plus a ton more. 360 Verify does property checking with coverage.
360 Quantify does a full formal coverage of your code and SVAs. 360 Safety injects
faults into device code to see if it recovers from an operational fault in the
field, and still works. SystemC App Connectivity XL App sees if your 1 billion
gate chip is interconnected properly. Their 360 Trust tool sees if any
HW security holes. PortableCoverage App measures coverage. FPU App does formal
on IEEE 754 floating point. 26262 FMEDA tool does safety metrics (SPFM, LFM, PMHF).
And their RISC-V Verification App does zero bug escapes and guarantees full
compliance with the ISA. It also does RISC-V compliance, SEE/MEE analysis, FPU,
mutation analysis, transactional assertions and Gap-Free. Tight with QuestaSim.
Plus the 10 old Mentor Questa Formal formal Apps for X-checking, RTL checks,
coverage, assertion checks, property generation, CDC, connectivity checks, post-
silicon, register checks, unreachability; plus SLEC for safety-critical designs.
"ISO 26262, baby!" Marvell, Microsoft, Samsung, Cypress, Infineon, Nokia, Mediatek.
(booth 2521) Ask for Chris Giles. Freebie: espresso & beer
Siemens Questa Verification IQ (VIQ) is Sawicki's snarky reply back at
Anirudh's CDNS Verisium launch. Questa VIQ does "data driven verification with
predictive and prescriptive analytics" (plus AI voodoo) "to accelerate closure,
accelerate debug turnaround time, and provide regression efficiency."
(booth 2521) Ask for Mark Olen. Freebie: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
Real Intent Ascent Lint RTL and netlist rule checking and sign off.
Certified by TUV SUD for ISO-26262 (TCL2). Has high impact rules for
syntax, semantic, and style checks for low noise and ease of debug.
Integrated debugger. Rule configuration editor has severity config and
annotations, categories, filters and searches.
New is it does "total TAT minimization from start to sign-off." Supports
multiple rule sets in a single run to verify IP and new RTL in ONE run.
New targeted debugger shows related violations in the same proximity.
Also new is duplicate violations are rolled up into a group presentation.
And the user can now define four custom levels of severity. Ascent Lint
is used by Google, Hailo, Dream Chip, Alif Semiconductor, Esperanto, Groq
(booth 2526) Ask for Lisa Piper. Freebie: LED pen
Real Intent Ascent AutoFormal identifies RTL design bugs early. 10X
speedup & 3 million gate capacity. It extracts RTL "implied intent"
checks, runs formal analysis, & determines root cause errors.
Detects FSM deadlocks, dead code & range violations, etc.
(booth 2526) Ask for Lisa Piper. Freebie: LED pen
Ausdia Timevision SOC Budgeter handles the SDC time budgetting
across hierarchical boundaries. Uses SDFs, timing reports and physical
data (LEF/DEF) to produce and manage accurate timing budgets for the
blocks used in hierarchical implementation flows.
Ausdia Timevision SdcCheck does 200 checks. "your SDC + checking it's intent."
MMMC constraints, Verilog/SystemVerilog/VHDL, IEEE P.1735 encrypted RTL.
Precise file/line backtracking pinpoint in your source RTL/SDC issues.
(booth 2310) Ask for Sam Appleton. Freebie: frisbees
Excellicon ConMan formally crafts hierarchical constraints for
multi/merged mode SDC, promotion, clocking analysis. Rivals Ausdia
and Fishtail. 500+ M inst. Concert EQ is equivalence checking for
Top2Block, Top2Top (1D2S, 2D2S, 2D1S, SDC2ETM checking). Does ECO
changes, cloning, decloning, logical restructuring etc.
Excellicon ConTree does pre-CTS analysis of clocking structure for
proper clock skew groups, automatic creation of anchor buffers and
creation of CTS file. In post-CTS phase, verifies CTS for lowered
clock latency and skew.
Excellicon ConCert verifies timing intent & structural exceptions
using SVA+/formal. SDC, CTS, demotion, equiv checking. They added
timing budgeting and exceptions toolboxes to ConCert this year.
LG, Samsung, Marvell, Renesas, Qualcomm, Western Digital, Maxim, ST.
(booth 2520) Ask for Himanshu Bhatnagar. Freebie: dice cups
Synopsys Timing Constraints Manager (formerly FishTail) is used for promotion and
demotion of constraints. Takes RTL or gate-level netlist and abstracts only the
required behavior and structure with respect to the task being performed.
(booth 2441) Ask for Rimpy Chugh. Freebie: pens & coffee
Real Intent Meridian RDC finds messy reset metastability & glitch
problems. Categorizes violations, has minimum noise. Claims in
benchmark vs. rival it had MUCH few violations (200 vs 500,000),
and was 8X faster (45 min vs 6 hours). Parallel & hierarchical.
Rivals SpyGlass RDC, Questa RDC. 200M gate full RDC in 9 hrs.
Claims 20% faster runtime and 30% better RAM utilization. Improved
viewer, does save-restore incrementals, can now do targeted RDC runs
for fast debug. Used by Groq, Esperanto, Google, Hailo, Dream Chip
(booth 2526) Ask for Sanjay Thatte. Freebie: LED pens
Real Intent Verix SimFix detects & corrects X-pessimism in gate-level
sims, enabling gate-level functional sign-off. Did 100M to 350M nets.
Real Intent Meridian RXV does X-impact analysis on RTL to avoid
messes with reset schemes, diverse IPs. Shows X-optimism causing
design errors. NO simulation vectors, nor coverage analysis nor
simulation is needed. Rivals Synopsys VCS Xprop, Cadence JasperGold.
(booth 2526) Ask for Sanjay Thatte. Freebie: LED pens
Amiq Verissimo is like a Spyglass linter but just for System Verilog
testbench code. "200+ checks in assertions, dead code, language
pitfalls, code maintainability, and UVM methodology guidelines."
It can auto-correct failures, and compare reports and tracking progress
Samsung, Cisco, Qualcomm, Xilinx, Toshiba, Broadcom, Nvidea, NXP.
(booth 1410) Ask for Cristian Amitroaie. Freebie: chocolates
Siemens Visualizer (formally Avery SimXACT) automatically find X bugs
in RTL and eliminates false X's in gate-level simulation. Has gated
clock X pessimism analysis and auto generated fix deposits. It competes
with Synopsys Verdi and Cadence SimVision/Indago/Verisium. Siemens
QuestaSim/Veloce/Symphony now ships with Visualizer. "Gate simulation
bring-up productivity is more than fixing false Xs!" Broadcom, Nvidia,
MediaTek, Qualcomm, Western Digital, Cavium, HPE -- and 5,000+ others.
(booth 2521) Ask for Mark Olen. Freebie: espresso & beer
Siemens Austemper KaleidoScope does mixed-signal fault injection as
functional safety tool. Does ISO26262 automotive stuff from OneSpin.
It rivals Synopsys Z01X, Cadence Xcelium Safety. KaleidoScope does
fault injection campaigns to detect the faults. Samsung, Rambus users
(booth 2521) Ask for Ann Keffer. Freebee: espresso & beer
SILICON LIFECYCLE MANAGEMENT
3.) Synopsys Silicon Lifecycle Management (SLM) is SW plus embedded DW IPs to do
SLM of your chip. SLM In-Chip Monitor IP tracks your chip's analytics on every phase
of the silicon lifecycle -- from initial design, to manufacturing, to in-field data.
It does pre- and post-silicon analytics, plus hooks with Synopsys TestMAX. Users
are Intel, Marvell, Microsoft, Qualcomm, ST, Alibaba, ARM, Google, Amazon, MediaTek,
Cisco, ST, Socionext, Marvell, Bosch, Arbe Robotics, Denso. The Synopsys SLM rivals
are Siemens Tessent, Proteantecs, and PDF Solutions Exensio/Cimetrix. (Not sure but
it looks like much of Synopsys SLM is a deep rebranding of Synopsys SiliconMAX.)
NEW! -- Synopsys SLM HSAT IP takes PCIe and USB interfaces to be re-used for high-
bandwidth production scan test. Also manufacturing scans in-system. Also later
in-field scans, to find structural degradation during the device's lifetime.
NEW! -- Synopsys SLM SHS IP automatically creates a hierarchical IEEE 1500 network
to access and control all IP/cores at the SoC level. It's a network for all SLM IPs
on-chip like PVT monitors, sensors, clock delay monitors plus XLBIST -- plus SMS as
well as chiplet interconnects like IEEE 1838. ST, Socionext, Marvell, Bosch users.
(booth 2441) Ask for Ash Patel. Freebie: LED pens & coffee
---- ---- ---- ---- ---- ---- ---- ---- ----
Siemens Tessent SLM is also SW plus embedded IP to track reliability/performance of
your silicon/package/PCB as it goes through its full lifecycle -- you know, SLM stuff.
Siemens Streaming Scan Network (SSN) is an embedded "test data super highway" IP inside
your chip. "All SLM starts with test -- and our SSN is the backbone that drives
packetized 100% payload scan data to your chiplet or multi-die design." DFT planning
is decoupled from design for faster TAT. SSN cuts your power profile by reducing
IR-drop. It tests identical cores with on-chip compare. Lets you tune your clock
timing for fast silicon bring-up. SSN is a beginning-of-life SLM tool. It's about
catching defects and scan testing early -- also while trying to suss out early
manufacturing & aging defects, too. Intel, Amazon, Broadcom, Qualcomm, Samsung, ARM
Siemens Tessent MissionMode is on-chip infrastructure to enable chips to test and
diagnose themselves at any point during functional operation and throughout their
silicon lifecycle. It has system-software based access to any test (and diagnosis)
within an SoC. Makes ISO 26262 possible. Does long-term reliability requirements
for many types of devices beyond just automobles like 5G base stations, satellites,
and aircraft cockpit electronics. Tessent MissionMode is a late-in-life SLM tool.
Siemens Tessent Embedded Analytics is also a bucket of monitor IP plus software that
"non-intrusively observes if your SoC functionally performs as it was meant to."
Full visibility in HW/SW interactions in deployed systems. Tessent EA is about
answering functional HW/SW questions like "why is new version of my SW now running
so slow?" or "why did my system hang in reboot?" Tessent EA is the quintessential
definition of a late-in-life SLM tool. Seagate, Kalray, Picocom users.
(booth 2521) Ask for Lee Harrison. Freebie: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
MAYBE? -- I got very specific hints that a Cadence SLM was coming from slides at
CadenceLive'24 -- in the middle of all that buzz about "Digital Twin" ...
"Digital Twin" is the stealth hot-new-thing at CDNS and SNPS this year
... but don't know if Anirudh will be stealth chatting Cadence SLM at DAC'24 or not.
(booth 1511) Ask for Anirudh Devgan. Freebie: CDNS SLM rumors (maybe?)
---- ---- ---- ---- ---- ---- ---- ---- ----
NEW! -- Keysight ELM HUB guides HW engineering teams from concept to silicon design,
enabling workflow and IP management, reuse, security, and traceability. I thought
it was a Silicon Lifecycle Management tool until they said ELM HUB competes against
the IC Manage Global Design Platform XL tool. "PLM tools focus manufacturing parts
bill-of-materials (BOM) and treat the silicon engineering lifecycle (concept, design,
verification, and test) as a black box. Keysight ELM HUB gives design teams
granularity to manage the silicon design engineering lifecycle successfully." WTF???
Silicon? Check... Lifecycle? Check... Manage? Check...
I'm bumping ELM HUB out of the DDM TOOLS category and into the SLM TOOLS category.
BAE Systems, Boeing, Allegro Microsystems, and Berkeley National Labs use ELM HUB.
(booth 1501) Ask for Amit Varde. Freebie: stress balls
EMULATION / ACCELERATION / PROTOTYPING
4.) NEW! -- Cadence Palladium-Z3 is Anirudh's new processor-based HW emulator based
on his hot new uP 5nm chip -- and it's a serious blow against the new Siemens
Veloce Strato CS -- who's uP only updated to a new 7nm chip. ("D'oh!")
Every chip designer deep down knows the shame of being at 7nm when your competition
is at 5nm... ("Ouch.") Anyway, this new Palladium-Z3 scales to 48 billion gates.
And it claims to have a 50% runtime improvement over the olde Palladium-Z2.
Z3's Modular Compiler compiles an 8 billion gate netlist designs in 5 hours. New
this year, the new Palladium-Z3 does 4-state emulation! Also has "full vision"
debugging, plus record/replay. Upper limit is 2,304 simultaneous users, but it's
job scheduler does dynamic job relocation so users can prioritize workloads.
Comes in air or water cooled options -- but most new Z3 installations are water
cooled. The old Z2 "Dynamic Duo" compiles with Protium X2 got #5 Best of 2020.
To follow that tradition, this new Z3 says it's "Dynamic Duo II". Like everyone
else, the new Palladium Z3 has AI everywhere and does AWS/Azure/GCP cloud.
Nvidia and AMD are early Palladium-Z3 users -- they spoke at its launch!
(booth 1511) Ask for Michael Young. Freebie: lotto stamp
NEW! -- Cadence Protium-X3 is an FPGA based prototyper (using the new Xilinx VP1902)
that can scales up to 48 billion equivalent FPGA gates, "runs 3-5X faster than
Palladium-Z3", and does super fast HW/SW sims up to 100 Mhz. Yay, VP1902! It
has debug aimed at software workloads including, SVA with lightweight mode, Save and
Restore, and FullVision for 100% signal visibility without pre-specifying probes.
The renamed "Dynamic Duo II" compiles with Palladium-Z3 is a very big selling point
for Protium-X2 and -X3. (See Best of DAC 19 #1a) Nvidia & AMD are early -X3 users.
(booth 1511) Ask for Michael Young. Freebie: lotto stamp
CDNS Palladium & Protium Cloud to add peak capacity to you Palladium/Protium runs.
(booth 1511) Ask for Bennett Le. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
NEW! -- Siemens Veloce Strato CS is Jean-Marie's processor-based HW emulator; scales
up to a whopping 40 billion gates. Strato CS's new 7nm uP chip is a great jump from
it's prior 28nm uP -- but Anirudh's got a 5nm uP in his new Palladium-Z3. Ouch!
How this new Veloce Strato CS wins is it's air cooled (while the new Z3 needs to be
water cooled) because Jean-Marie's new Strato CS uses 1/5th power Anirudh's new Z3
uses -- a big selling point for certain customers. (ESNUG 567 #3) And the new
Strato CS does a "Dynamic Duo"-type-of-co-compile with Veloce Primo CS, mimicking
how Anirudh's HW works. "So let's talk about the total cost of ownership now, OK?"
(booth 2521) Ask for Vijay Chobisa. Freebee: beer
Siemens Veloce Apps are tight w/ Ansys Apache PowerArtist. Its RTL power reduction
analysis is 4.5X faster. There 8 other Veloce Apps: Coverage, Assertion, ICE, DFT,
Deterministic ICE, Power, SW Debug, and Ixia Virtual Network App. ST, Broadcom.
(booth 2521) Ask for Vijay Chobisa. Freebee: espresso & beer
NEW! -- Siemens Primo CS is like new Cadence Protium X3, but for new Siemens Veloce
Strato CS. Also based on hot new VP1902. Does HW/SW runs to 25 Mhz. Air cooled.
40 billion gate capacity. Easy co-compile with Veloce Strato CS and Veloce proFPGA.
(booth 2521) Ask for Zaid Rodriguez. Freebee: espresso & beer
Siemens Veloce proFPGA is like SNPS HAPS but based in Germany. Used to mix/match
old Xilinx Virtex 7 330T to 2000T to Altera Stratix 10. 600 M ASIC gates. 20 Gbps.
In 5 years they shipped 1251 units to 121 customers. Now you can add in hot new
Xilinx VP1902's to the mix to get 100 Mhz runstimes at 4 billion gates per rack!
(booth 2521) Ask for Juergen Jaeger. Freebie: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
NEW! -- Synopsys Zebu EP2 still uses dinosaur olde Xilinx VU19P to do HW/SW runs on
noticeably smaller 5.6 billion gates at 25 Mhz. (See ESNUG 596 #5) Meh. But it gets
really interesting when it's teamed with the new HAPS-100 (also based on old VU19P's)
because then -- through the magic of asynchronous clocking -- that 5.6 billion gate
HW/SW run accelerates to a screaming fast 450 Mhz! Ravi's roadrunner strategy is
this: "We're small. And devious. And blindingly fast!" (Ravi says he's sees
customers dump the CDNS and Siemens way of emulation/prototyping and instead
they're going "all in" on his ZeBu/HAPS approach.) And he even has a Zebu Cloud
option if you want to add peak capacity to your Zebu runs. "BEEP! BEEP!"
(booth 2441) Ask for Himanshu Baath. Freebie: pens & coffee
VIRTUOSO & RIVALS
5.) NEW(ISH) -- Cadence Virtuoso Studio is massive amounts of AI pumped into Virtuoso's
full custom/analog monopoly. Studio ADE kicks off 1,000s of parallel SPICE runs &
layout throughput is 100,000s of single 5/4/3/2nm transistors and the new GAAFets.
Built-in Pegasus DRC/LVS for interactive signoff DRC that cuts TAT 20% by "quickly
detecting and fixing issues before they become a problem." Deep hooks into Cadence
AWR Microwave Office IP for RF/microwave/mmWave and heterogeneous system designs
(which is again more evidence that Beckley is gunning for Keysight's RF niche.)
Virtuoso Studio has deep hooks in Spectre, Spectre-X, Spectre-FX, and Spectre FMC
Analysis for "10,000X speedup in design space exploration for 3- to 6+-sigma
variation analysis with Monte Carlo sims. New this year, Beckley's Virtuoso Studio
is in a celebrity deathmatch with Shankar's Custom Compiler over analog migration.
DAC'23 Troublemaker Panel: Beckley claims Virtuoso does 80% analog migration
Whoa - Shankar is now seriously gunning for Tom Beckley's Virtuoso empire
Whoa - hands-on user benchmark confirms SNPS ASO.ai gets 50% analog migration
Virtuoso Studio users Samsung, ADI, Nvidia, MediaTek, Qualcomm, Intel, NXP, and TSMC.
(booth 1511) Ask for Steven Lewis. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
Synopsys Custom Compiler is Aart's 2nd attempt on Beckley's Virtuoso monopoly. The
1st try was Custom Designer (which flopped.) CC runs the old Laker3 router plus
Ciranova Helix plus some "assistant features" to generate many different layouts
all off of one schematic -- just sort of like how Cadence Pulsic Animate works.
New this year: Shankar is using an AI enhanced version of his Custom Compiler
(driven by his SNPS ASO.ai) in order to flank Beckley's new Virtuoso Studio in
the 10nm-7nm-5nm-3nm-2nm-1nm analog migration niche.
Whoa - Shankar is now seriously gunning for Tom Beckley's Virtuoso empire
They claim this "Custom Compiler is 5X more productive" -- whatever that means -- and
it does "intuitive layout automation" plus "has Synopsys PrimeWave to help engineers
across 1000's of simulations to find the outlier waveform behavior quickly for design
centering and optimization" plus it does "schematic and layout-aware design migration
to save weeks of manual and iterative effort." Shankar really is gunning for this.
He has 3 SNPS R&D engineers for every $1 M in CC sales -- compared to Beckley
who only has 0.9 CDNS R&D engineers for every $1 M in Virtuoso sales. Shankar is
tripling down on his CC/ASO.ai per-capta-spend to beat Beckley. Problem is Beckley's
Virtuoso Studio is used in 8 of the Top 20 Big Boy logos for analog migration; while
so far -- as of 6/18/2024 -- I can't find even one Top 20 Big Boy logo using CC/ASO.ai
for production quality analog migration. Maybe this will change at this DAC'24?
(booth 2456) Ask for Hany Elhak. Freebee: pens
---- ---- ---- ---- ---- ---- ---- ---- ----
Cadence Pulsic Animate does an AI-enhanced layout of analog (transistor level)
designs, with no constraints, no scripting, no programming required. Multi-threaded.
It makes 100's of fully PnR-ed layouts in minutes from an OA schematic (vs. 2-3 weeks
single layout in olde Virtuoso). Last year it cut 40% PnR runtime 40% for Ricoh.
Now super tight with Virtuoso. Did 60-80% faster analog block PnR for Silicon Labs.
Users ADI, ST, NXP, TI, Renasas, Medtronics plus 300? other logos. Animate's wildly
popular; which is why Shankar mimics Animate in his SNPS Custom Compiler offering.
(booth 1511) Ask for Steven Lewis. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
Siemens Solido Design Environment is Solido Amit taking on the Virtuoso ADE
monopoly by launching Solido DE -- a cloud-ready, comprehensive AI-powered
environment for analog, memory, and std cell flows, with integrated variation-aware
design (and verification as well) with an integrated modern wave viewer, Solido
Waveform Analyzer.
It's a SPICE simulation environment like Virtuoso ADE that runs Siemens AFS, CDNS
Spectre, and SNPS HSPICE/FineSim SPICEs. (It's only a DE to fire of SPICE runs.
Siemens schematic capture and layout by Tanner S-Edit and L-Edit. Virtuoso does
it with Composer and Layout Editor.)
Also Solido DE "extends AI deeper into custom IC design/verification using
Additive AI and Assistive AI for a disruptive impact." Claims 1000X+ speedup with
better accuracy. TAT is cut by weeks! It competes with Cadence Virtuoso ADE and
Virtuoso Variation, Synopsys PrimeWave, Silvaco VarMan, and MunEDA. As part of the
distro, Solido DE is used by 90+ semi houses like Nvidia, SK Hynix, ARM, ST, Micron,
Allegro, Ametek, Crypto Quantique, Silicon Creations, Samsung, and Infineon.
(booth 2521) Ask for Wei-Lii Tan. Freebee: espresso & beer
Siemens Insight Analyzer finds sources of leakage currents (analog, digital, and
parasitic) with static circuit checking. Rivals Synopsys CCK and Aniah OneCheck.
(booth 2521). Ask for Carey Robertson. Freebie: espresso
Siemens Calibre RealTime Custom does instantaneous sign-off DRC checks and fixes
inside Virtuoso, Laker3, Custom Compiler. Same deck, same results as batch Calibre.
2-5X productivity improvement when fixing DRCs in 180-2nm nodes. Double/triple
patterning, preferred metal direction, density checks, pattern matching and voltage-
aware DRC. Has cells/blocks-to-macros DRCs to automatically launching batch
Calibre jobs. Rivals Cadence iPVS. Qualcomm, Broadcom, SiLabs.
(booth 2521) Ask for Joe Davis. Freebie: espresso & beer
Siemens Tanner is OA-based S-Edit schematic capture, L-Edit custom layout, and
T-Spice SPICE. Founded 1988. "Cost effective" prices. The old HiPer Verify DRC
was replaced by Calibre DRC. Pyxis is in it, too. Does 16/12nm now! MEMS designers
like Obsidian, Microgen, Innotime, Velankani, Eesy IC, Microdul AG, PragmatIC users.
(booth 2521) Ask for Jeff Daspit. Freebee: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
Silvaco Expert is a hierarchical IC layout editor. Schmatic driven. 10 Gig GDSII
loads in "minutes". Uses Calibre Interactive for DRC "on the fly". Rapid pan/zoom.
Equal resistance router. OA and interop PDKs (iPDK) makes design migration easier.
And WTF???!! Silicon Creations uses it for 7/5nm FinFET? Silvaco doing 7/5nm?!?
Also Silvaco Clever 3D RC field solver does BEOL/MEOL parasitic extract.
(booth 1539) Ask for Babak Taheri. Freebie: tape measure
Silvaco Cello FinFET fine tunes std cells for slow transitions, power, voltage.
Also multi-bit cells (saves 25-30% dynamic power, 20-25% leakage), CPU/DSP datapath
(8-14% less area). 16/14/10/7nm. Also does coloring, self aligned MOL, template
based cell creation. (booth 1539) Ask for Babak Taheri. Freebie: tape measure
LibTech LibChar does std cell, IO, SRAM characterization & modeling.
Now does PLLs. (booth 1510) Ask for Mehmet Cirit.
Movellus PLL/DLL/LDO Generator is kind of weird because it creates
*digital* versions of *analog* IP. In this case, it's PLL's, DLL's,
and LDO's. Why? Because then you can use *digital* synthesis, STA,
PnR on your PLL/DLL/LDO -- making them portable across nodes, and
you can do scan/ATPG/DFT on your PLL/DLL/LDO, too! (See ESNUG 582 #2)
So far at TSMC 16nm and Mo is working on 7nm. Intel Capital funded.
(booth 2311) Ask for Mo Faisal. Freebie: chocolates
Keysight Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Does hierarchical.
Works with DesignSync & IC Manage. Can suppress cosmetic changes.
Batch mode to run diffs in the background and save state for later.
Intel, Broadcom, Qualcomm, Infineon, Bosch, Marvell, Toshiba, TSMC.
(booth 1501) Ask for Niels Fache. Freebie: pens
Empyrean Skipper does super fast layout review, analysis, debug,
layout IP protection. 1TB GDSII. Marvel, Hisilicon, Sandisk.
(booth 2513) Ask for Jason Xing. Freebie: fluffy toy
Keysight ADS and GoldenGate SPICE is for silicon RF IC design and
simulation. iPDK PyCell & TSMC iRCX support, intuitive layout, does
electro-thermal on windows, harmonic balance & circuit envelope
converges faster. Qorvo, Skyworks, Broadcom/Avago, Qualcomm users.
(booth 1501) Ask for Niels Fache. Freebie: pens
Keysight SOS ADS does design data management for RF engineers using
Keysight Agilent ADS. Northrop, IDT, Quorvo, Rohde & Schwarz, Inphi
(booth 1531) Ask for Niels Fache. Freebie: pens
3D-IC / CHIPLET / MULTI-DIE DESIGN TOOLS
6.) Cadence Integrity 3D-IC used for simultaneously designing and analyzing multiple
chiplets. Innovus/Virtuoso/Allegro to do system-level plan/implement/analyze
early floorplan synthesis, cutline partitioning, concurrent 3-D placement,
3-D dis-aggregation, die-interposer-package design with on-chip and off-chip
signoff analysis for 2.5D/3D stacked die designs. Has Cadence 3-D Blox advanced
features and multiple foundry support. In-design electro-thermal, SI/IP,
multi-die extraction, and static timing analysis. It competes against the
SNPS 3D-IC Compiler/ANSS Redhawk-SC Partnership, and SNPS 3DSO.ai.
Samsung, TSMC, UMC, Meta, Microsoft, Tesla, GUC, Socionext, Fraunhoffer, Sony,
Broadcom, and Rivos are users. Cadence Integrity 3D-IC was "used to design
and verify the wafer-scale packaging for the Tesla DoJo supercomputer."
(booth 1511) Ask for Vinay Patwardhan. Freebie: lotto stamp.
---- ---- ---- ---- ---- ---- ---- ---- ----
Synopsys 3D-IC Compiler and 3DSO.ai is Sassine's answer to Cadence Integrity 3D-IC.
It does early architecture exploration, system validation, die-package co-design,
die-to-die connectivity, and tweaks for manufacturing and reliability. It targets
3DHI designs, with "billions of connections and routing." It's super tight with
PrimeTime for 3D static timing analysis, and Ansys for thermal, EMIR and
signal/power integrity. 3DSO.ai is the AI part that drives everything underneath
it for 2.5D and 3D multi-die designs. AMD, Intel, Cisco, Google, Samsung, GUC
(booth 2441) Ask for Jim Schultz. Freebie: pens & coffee
---- ---- ---- ---- ---- ---- ---- ---- ----
NEW! -- Siemens Innovator 3D-IC is a unified cockpit for all the Siemens tools used
in design planning, prototyping, and predictive analysis of "heterogeneously
integrated chiplets, interposers, and package substrates using a "Digital Twin"
unified data model of the complete semiconductor package assembly." Certified
for the Intel Foundry EMIB packaging platform. This tool came about because
Joe Sawicki in 2022 was bullshit over Tom Beckley bragging on the DAC Troublemakers
Panel that -- at the time -- Cadence had the only working integrated 3D-IC flow
back then. (See ESNUG 592 #5)
"Beckley showed 8 cherry picked 3D-IC design tasks, for his 8 Cadence
tools. Whereas a true, actually proven 3D-IC flow -- our Siemens flow
for 3D-IC -- has 21 3D-IC design tasks, that involve 24 Siemens tools!"
Now -- two years later -- at this DAC'24, see how Siemens Innovator 3D-IC cockpit
is used to design Intel's EMIB with tons of silicon interposers embedded the package
substrate. Users are Qualcomm, Micron, MediaTek, Broadcom, Facebook, Samsung, Amkor
(booth 2521) Ask for Mike Walsh. Freebee: espresso & beer
Siemens Tessent Multi-Die is DFT for chiplet/multi-die designs in 2.5D or 3D.
It supports 2.5D flows with boundary scan-based interconnect die-to-die test. It
"enhances 3D flows with IEEE 1838 compliant PTAP/STAP and it uses silicon-proven
Tessent SSN as a flexible parallel port. It "extends proven hierarchical DFT
methodologies to 3D-IC designs." Tessent Multi-Die lets you port 2.5D chiplets
over to a 3D-IC implementation. Because "using SSN bus is the easiest way to
get in and out of chiplets that are in a stack." TSMC and Broadcom users.
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
RedHawk Analysis/Fusion PnR Partnership is a super tight integration
of RedHawk-SC with Primetime-SI to work inside Sassine's Fusion Compiler.
Now with lots of AI/ML stuff thrown in. That's 2 EDA vendors with
3 different db's under one hood; a difficult interop but now it works!
Does 3D-IC, machine learning, AI. "We added Tweaker ECO to this, too!"
(booth 1308) Ask for John Lee. Freebie: stuffed animal
COMPLETE CDC SIGN-OFF
7.) Siemens Questa CDC does post-implementation, gate-level CDC analysis and glitch
detection for signoff. Low noise results due to focus on implementation-based
causes. High QoR, high scalability. ISO 26262. Has gate-level stuff for FPGAs.
New this year are it does hierarchical abstractions to speed-up the CDC analysis.
"Cloud and AL/ML everywhere, too!" Mediatek, Marvell, Cypress, AMD users.
(Booth 2521) Ask for Chris Giles. Freebie: espresso & beer
Cadence Jasper now has 17 formal Apps. One of them does CDC.
(booth 1511) Ask for Pete Hardee. Freebie: lotto stamp
Siemens Questa Formal has 11 formal Apps. One of them does CDC.
(booth 2521) Ask for Chris Giles. Freebie: espresso & beer
Real Intent Meridian CDC for low noise RTL CDC. Samsung used it's
hierarchical flow and cut # of CDC violations to review by 95-98%
and engineering time by 70%. Claims runtime cut by 8X, and memory
cut by 4X for 800M gate chip with 103 clock domains. New data
model cuts memory by 30%, noise by 5-10X. Dynamic CDC protocols.
New this year -- flat and hierarchical multimode sign-off, multimode
-aware dynamic CDC models, low noise sign-off (including handshake
and interface handling, glitch detection, and reconvergence), root
cause groups 10X faster, incremental iterations in minutes instead
of hours. Samsung, Google, Nvidia, Groq, Western Digital are users.
(booth 2526) Ask Vikas Sachdeva. Freebie: LED Pen.
Ausdia Timevision-CDC does block/fullchip CDC analysis on RTL or
gates using SDC constraints only -- so it can verify your actual
clock groups as being CDC-safe. 500 M inst with 1000 clocks in
8 hours. GUI user does full tracing. Handles flop duplication,
retiming and merging. Qualcomm, Nvidia, Broadcom, Mediatek, ARM
(booth 2310) Ask for Sam Appleton. Freebie: frisbee
SPICE / AMS / CHARACTERIZATION
8.) Cadence Spectre-X claimed to be 10x faster than old Spectre thus, if true, it was
going to trash the entire SPICE ecosystem. The truth is Spectre-X did well keeping
up with Siemens BDA AFS, but it didn't wipe out AFS at all. Spectre-X's big thing
is its massive distributed computing plus it does AWS/Azure/GCP clouds.
From last year -- "Spectre-X is 10X faster with 5X more block level capacity at
golden SPICE accuracy." It loves complex analog, mixed-signal and RF blocks. Does
millions of post-layout parasitics with 10X more performance and 5X capacity.
Scales up to 256 cores and can leverage GPU hardware in a compute farm or on the
cloud. Spectre-X does mixed-signal with Xcelium digital (with RTL digital blocks
mixed with SPICE and/or behavioral model representations for analog blocks.)
Also from last year, Spectre-X seemed to gunning for Keysight's RF/microwave niche.
Spectre-X has an RF extension to support harmonic balance, shooting newton, envelope
and other RF/high frequency analyses for fast and accurate verification of high
frequency analog & RF circuits. These RF Spectre XDP runs are on 256 cores across
multiple machines to allowing for bigass SPICE runs of post-layout RF/microwave
designs. For RF it does enhanced load pull analysis for high-speed I/O design.
MediaTek, Renesas, Siliconworks, Texas Instruments, Microsoft, AMD.
(booth 1511) Ask for Steve Lewis. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
NEW! - Siemens Solido SPICE Simulation Suite adds 3 new SPICEs -- Solido SPICE,
Solido FastSPICE and Solido LibSPICE -- in a suite with BDA AFS, Eldo, and
Symphony. Does analog, RF, mixed-signal, library IP, 3DIC designs. Works closely
with Calibre sign-off, Tessent Test, and Siemens' Electronic Board System solutions.
Over 300 companies including Nvidia, Silicon Creations, Qualcomm, NXP, Infineon,
Semtech, Mixel, Microsoft, Ametek, Sony, Silicon Labs, Mediatek, LG, Skyworks.
(booth 2521). Ask for Pradeep Thiagarajan. Freebie: espresso
Siemens BDA AFS claims is 2x faster than parallel SPICE simulators. 20+ M elements.
TSMC 5/4/3/2nm certified. 2X faster. "We do a boatload of AI/ML stuff now, plus
we're in AWS/Azure/GPC cloud." and "Our hot new AI stuff is going to give the other
SPICE guys nightmares." AFS with Solido, has 10x faster throughput for OCV vs.
other SPICEs. BDA ACE for analog characterization runs. AFS Mega does SPICE of
100+ M element mega arrays like memories. In 2020, Joe Sawicki said ...
Sawicki on his "free" AFS-XT being 5x-10x faster than Spectre-X
which resulted in ...
Users chose Sawicki's AFS-XT SPICE gambit as Best of 2020 #1a
So now Siemens AFS has over 235 customers like Samsung, MediaTek, Intel, NXP,
Broadcom, Qualcomm, SiLabs, Fujitsu, Analog Devices, Sony, LG, and Skyworks...
(Booth 2521) Ask for Francois Le Grix. Freebie: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
Synopsys PrimeSim bundles HSPICE, PrimeSim SPICE, PrimeSim Pro, and PrimeSimXA.
PrimeSim is GPU-accelerated SPICE and FastSPICE. Good for big problems like
"memory full-chip + PDN" or "full-chip CIS w/ 1K+ column ADC". Does pre-silicon
reliability analysis (early, normal, end-of-life failures) for Synopsys SLM.
Samsung, SK Hynix, Nvidia, Intel, Broadcom. (booth 2441) Ask for Hany Elhak.
---- ---- ---- ---- ---- ---- ---- ---- ----
Cadence Spectre-FX does FastSPICE. Claims 3X faster for "advanced partitioning
and RC reduction" and "handles several 10s of millions of RC parasitics and
supports post-layout DSPF and extracted SPICE formats." Transient simulations up
to 32 cores. Competes against Synopsys PrimesimPro and PrimesimXA. Spectre-FX
also does mixed-signal with the Cadence Xcelium digital simulator. MediaTek,
Renesas, SK hynix, Samsung Foundry, JVC Kenwood, DB GlobalChip use Spectre-FX.
(booth 1511) Ask for Steve Lewis. Freebie: lotto stamp
Cadence Liberate Trio now does aging, Liberate Insight validation and ML prediction.
Rivals are Siliconsmart/PrimeLib, Siemens Solido, Kronos, and Predictor (Mentor).
Maxlinear, Samsung, AMD, ARM, ST, LG, Renesas, TI, Marvell, NXP, ZTE, XFAB users.
(booth 1511) Ask for Steve Lewis. Freebie: lotto stamp
Cadence Spectre FMC Analysis does variation aware analysis of PVT corners
on your chip. "3 to 6+ sigma yield with 10X speedup over brute force
Monte Carlo analysis." Does command-line and the Virtuoso ADE gui.
Compute farm or cloud. It works well with Liberate Trio and Tempus.
(booth 1511) Ask for Steve Lewis. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
NEW! - Siemens Solido IP Validation Suite does end-to-end silicon QA across all IP
design views and formats, as well as version-to-version IP qualification. Includes
Solido Crosscheck with 300+ IP validation checks and works across 32+ formats
(Verilog/VHDL,.Libs, LEF, DEF, GDS, schematics, and more). New Solido IPdelta
does version-to-version IP QA for all design views and formats. Used at ST, Mixel,
Samsung, Microsoft, Renesas, MaxLinear, Rivos. Competes with Empyrean Qualib.
(booth 2521) Ask for Wei Lii Tan. Freebie: espresso
Siemens Solido Characterization is an AI-enabled, production-accurate
.lib generation/verification tool. "Speeds up library characterization
and verification by weeks, using artificial intelligence. Finds trends
and outliers across PVTs. Generates .libs for new PVTs instantly." For
std cell, memory, and I/O libraries. NLDM, CCS, CCSN, CCSP, ECSM, AOCV,
LVF. New powerful validation GUI. New APIs for lots of customization.
(Booth 2521) Ask for Jeff Dyck. Freebie: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
Silvaco SmartSpice Pro is Dave Dutton's push into the memory
fastSPICE market. Claims "true SPICE behavior but with much faster
generation of waveforms" and "2X speed-up on AMOLED panel and SRAM
designs with better waveform overlay results than other simulators."
Does 28/16/14/10/7nm. SmartSpice (golden), SmartSpice HPP (parallel).
Samsung and LG are users. SmartSpice PRO for SRAM simulation.
(booth 1539) Ask for Babak Taheri. Freebie: tape measure
Empyrean ALPS is a killer SPICE from a Chinese EDA company that
crushed FineSim/PrimeSim/Spectre-X in a 2022 user benchmark.
Empyrean ALPS benches 2.7X to 38.4X vs. FineSim/PrimeSim/Spectre-X
and Empyrean also kicked ass in 2020 with its ALPS-GT here with...
Empyrean ALPS-GT crushes Spectre-X and AFS-XT is Best of 2020 #1c
HiSilicon, Kilopass, Monolithic Power Systems, Ricoh, Toshiba are users.
(booth 2513) Ask for Jason Xing. Freebie: fluffy animal
LibTech TurboChar competes against SiliconSmart and Liberate to
do std cell, IO, and SRAM characterization and modeling. Has
"massive parallelism", fast LVF/AOCV, improved auto-configuration.
Claims it improves linearly with more CPS, "does not level off like
queueing methods". (booth 1510) Ask for Mehmet Cirit.
Silvaco Jivaro does netlist reduction for SPICE sim acceleration.
Multithreaded for DSPF/SPF netlists. Speeds up Spectre by 3X. More
accuracy. OA DM5 is supported. Silvaco Viso does quick analysis
of interconnect parasitics. Tight with Virtuoso. Silvaco Belledonne
does extracted netlist comparison -- for PDK optimization.
(booth 1539) Ask for Babak Taheri. Freebie: tape measure
Siemens Solido Variation Designer does variation-aware design for PVT
corners, 3 to 9-sigma Monte Carlo, hierarchical and sensitivity analysis.
Big thing is it cuts waaaaaaaay down on how many SPICE runs you need.
"We got cloud & AI everywhere, too!" Good for memory, std cell, analog/RF,
custom digital. TSMC, Broadcom, Nvidia, Huawei, Cypress, ARM, IBM users.
(Booth 2521) Ask for Jeff Dyck. Freebie: espresso & beer
Silvaco VarMan does Monte Carlo 3 to 8 sigma. Supports non-Gaussian.
Batch mode characteration of 100's of cells for you. 28nm FDSOI,
40 cells, 100 corners, Monte Carlo at each corner, 100's of measures,
took 173 mins using brute force MC and only 19 mins on VarMan. It
increases linearly to 6 sigma while claims Solido explodes hundreds
of times more to 6 sigma. ST Micro, Faraday, and Dolphin Integration.
(booth 1539) Ask for Babak Taheri. Freebie: tape measure
Empyrean XTime uses Big Data analysis to do "much faster accurate
Monte Carlo silicon timing sign-off." Does critical path, low
power and sensitivity analysis. Used for design margin recovery.
(booth 2513) Ask for Jason Xing. Freebie: fluffy animal
MunEDA WiCkeD was acquired by Cadence. (booth 1511) Ask for Andreas Ripp.
POWER / IR-DROP / NOISE / THERMAL for transistors
9.) Cadence Celsius -- is Anirudh's thermal solver in an electro thermal simulation
tool to rival Ansys IcePak and Siemens FloTherm for die design. "Simulate in
minutes designs that require hours in other tools, at the same level of accuracy."
Celsius 3x faster simulation/design cycle turnaround time (TAT), due data handling,
meshing, parallelization, and seamless in-design analysis with CDNS Allegro for
PKG/PCB, Integrity for 3D-IC/chiplets, Innovus for digital PnR, Virtuoso for
RFIC/full custom/photonics, and AWR Microwave Office for modules. Users are BAE,
Analog Devices, SatiXfy, ST, Bosch, Tower Semi, Rohde & Schwarz, Samsung, ARM.
(booth 1511) Ask for Yun Dai. Freebie: lotto stamp
Cadence Voltus does full-chip and 3D-IC EM-IR signoff. Has massively parallel flat
capacity "scales up to 1,024 CPUs" 1 B insts over 100s of compute CPUs. Taped out
multiple 100B+ PG node designs. Tight with digital tools (Innovus, Tempus, Pegasus),
and multiphysics solvers (Celsius, Sigrity, Clarity) for thermal and system power.
Customers boost EM-IR signoff producitivy by 10x when coupled with Voltus InsightAI.
Heard rumors MediaTek/Meta/Google/Amazon use it for AI chips. Voltus is TSMC 2nm
certified and "has multiple 3/5nm tapeouts. All good silicon. Customers happy.
"Now in TSMC 2nm ref flow." Nvidia, Samsung, MediaTek, Marvell, TI, ARM, Tesla,
Cisco, Amazon, NXP, TSMC, GF, ST, ON Semi, Renesas, and ADI are all Voltus users.
(booth 1511) Ask for Rajat Chaudry or Karan Sahni. Freebie: lotto stamp
Voltus InsightAI uses generative AI to predict and then auto repair IR-Drop issues
early. Rivals Fusion Compiler + RedHawk-SC combo. It's tight with Innovus, Tempus,
Pegasus, Quantus for DRC-aware fixes on IR-Drop issues. MediaTek, Cisco, ARM users.
(booth 1511) Ask for Rajat Chaudhry. Freebie: lotto stamp
Voltus-Fi does transistor-level noise/power signoff with Quantus QRC and MMSIM
inside Virtuoso. Both Voltus and Voltus-Fi are now TSMC 2nm. MediaTek, Cisco,
ARM, Samsung and SixSemi are users. Rivals Ansys Totem and Synopsys HSim-PWRA.
(booth 1511) Ask for Ben Gu of Steve Lewis. Freebie: lotto stamp
Cadence Clarity is Anirudh's direct assault against the Ansys HFSS full wave
solver empire. Cloud, massive parallelization, plus a "breakthrough new way to
solve the matrix", Clarity gets 10X faster speed using 12x to 32x less memory!
(ESNUG 586 #5). It has Ansys CEO Ajei Gopal in a defensive war. Samsung,
Maxlinear, Teradyne, Ambarella, Global Unichip, Baidu, Microsoft, Socionext users.
(booth 1511) Ask for Andrew Wang. Freebie: lotto stamp
Cadence Celsius EC (formerly 6SigmaET by Future Facilities) is
electronics cooling simulation SW. Lets mechanical engineers solve cooling issues
with CFD and "meshing technology". Fix cooling problems ASAP. Can analyze airflow,
temp, heat transfer in electronic assemblies and enclosures related to natural
convection, forced convection, solar heating, and liquid cooling. Rohde & Schwarz.
(booth 1511) Ask for Yun Dai. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
Siemens mPower -- IC signoff EMIR for analog, digital, and 3D-IC. It rivals Ansys
RedHawk-SC and Totem-SC, Cadence Voltus and Voltus-Fi. "Totem and Voltus-Fi can't
do dynamic EMIR and craps out at 1 million transistors; our mPower Analog can do
dynamic analog EMIR on 100 million transistors, and static analog EMIR on 1.5 billion
transistors". mPower Analog works with DSPF, extracted views, Calbre extraction,
Star-RC extractions, Spectre, AFS, Eldo, HSPICE ... "anything that outputs an FSDB",
while Voltus-Fi is locked into a CDNS-only flow.
On the digital side, an AI chip guy using mPower Digital did dymamic and static
digital EMIR at 7nm with "1064 RISC-V processors" (which I'm guessing is around 3.5
billion instances.) So it looks like MENT's plan is to attack Voltus and Redhawk on
capacity weaknesses, too. See ESNUG 590-06. Users are MaxLinear, Onsemi, Hammatsu.
(booth 2521) Ask for Joe Davis. Freebee: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
Ansys Apache RedHawk-SC is full-chip/3D-IC power integrity analysis and sign-off,
transients, simultaneous switching noise package/PCB with distributed processing.
It's the original Apache RedHawk with the huge loyal customer base -- but now with
lots of AI/ML thrown into your analysis. Last reported scalable to 32 machines
(256 cores). "500M insts with 8B resistors plus keeping flat simulation accuracy".
Elastic compute and claims "IR-drop in 6 hours on a 1 billion gate chip on a
16G machine" and "does 1000 scenarios overnight". Vector-based and vectorless.
Clock jitter. It was built on SeaScape ("Gear"). TSMC 7nm/5nm/3/2nm FinFET.
(booth 1308) Ask for John Lee. Freebie: stuffed animal
From a 7 year deal, Synopsys gets all its IR-drop, thermal, power analysis, and
CFD tools from their partnership -- now $31 billion acquisition -- with Ansys.
---- ---- ---- ---- ---- ---- ---- ---- ----
Synopsys Power Device WorkBench optimizes power transistors by simulating resistance
and current flow within complex metal interconnects. Optimize design parameters,
such as metal layouts and bond wire configurations. Insights into sensitivity,
current density, electromigration, and hot spots -- so process development and device
design groups can enhance power arrays without costly manufacturing iterations.
(booth 2521) Ask for Jim Schultz. Freebee: pens
DIGITAL P&R PLUS THEIR "AI DRIVERS"
10.) Siemens Aprisa (formerly Avatar, formerly Atoptech) is the distant 3rd place
PnR brother in a 3 brother PnR family. After many years of legal sturm und
drang, Aprisa is now a lawyer-safe ESNUG 592 #2 fiesty PnR brawler trying to
lock in a 2nm island inside the Innovus/Fusion Compiler "moat" before CDNS
and SNPS solve the 2nm chip physics problem themselves. It's a race to 2nm!
Ravi on Siemens' 14 new Aprisa PnR customers in only 12 months
At DAC'24, Aprisa PnR is definitely a "must see" because DAC is the only
non-CDNS, non-SNPS controlled open conference where you can see it.
TSMC/Samsung certified at 5/4/3nm; tight correlation pre- to post-route and to
Calibre sign-off. New AI-driven macro placement algorithm. Maxlinear says
Aprisa floorplan in 2 hours "compared to 3 to 4 weeks with competing tools."
Also new data bus algorithm for routing and skew balancing of 3D-IC HBM designs.
(Booth 2521) Ask for Alpesh Kothari. Freebie: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
Cadence Innovus PnR claims to be the #1 heavyweight champ of digital PnR. It's
rival is Synopsys ICC2/Fusion Compiler. Innovus claims to be #1 for 5nm and
"delivered the world's 1st production 3nm tapeouts." Now 2nm certified. Innovus
has "Smart Hierarchy" for "best TAT without sacrificing PPA." New this year is
it now has "backside routing" and "better AI optimization."
Last year, the CDNS R&D guys developed "Flash PG", a language to automatically
script production power/grid configurations that compiles in minutes. (Usually PG
definitions are ad hoc, done through the GUI and saved and replayed on later design
versions -- usually messy and runtimes can be long. "Flash PG" is a new language
to spec out your power grid going top down -- and you can compile it to new designs.
Lets users try out various PG combinations to dial-in IR-drop vs. area/congestion.
goals super fast.) Innovus + Joules also does glitch power optimization.
Innovus now hooks into Virtuoso Studio for "simplified mixed-signal designs."
So it's no surprise that Qualcomm, Nvidia, ST, Faraday, GF, MediaTek, ARM, Sony,
Broadcom, Toshiba, Freescale, Juniper, Renesas, Maxlinear, Intel, Spreadtrum, NXP,
Silicon Labs, Cypress, ImgTec, Realtek, Meta, MediaTek, Google. Related juicy
story: the chip inside the phone in your pocket was made with Innovus.
(booth 1511) Ask for Vinay Patwarhan. Freebie: lotto stamp
Cadence Cerebrus is the AI that drives CDNS Innovus PnR with reinforcement learning
to automatically optimize PPA. Used by "10 of Top 20 automotive, mobile and IoT
applications semi companies" and "5 of the Top 10 hyperscalers" Goes from 28nm
all the way 7/6/4/3/2nm with 350+ tapeouts. Has 60% better timing, and 40%
reduced leakage, and 10X TAT engineering productivity. Used by Nvidia, ARM,
Qualcomm, Google, Tesla, Sony, Mediatek, Renesas, Samsung, ST, Broadcom, Intel.
(booth 1511) Ask for Kumkum Bhatt. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
Synopsys Fusion Compiler and IC Compiler II are Sassine's two intertwined RTL-to-GDS2
digital PnR tools. ICC2 is older than FC. ICC2 has multiple internal db's while
FC has one unified internal db. Fusion Compiler claims 20% improved QOR and 2X
faster time-to-results. Fusion Compiler cockpit drives SNPS' RTL physical synthesis,
design planning, placement, clock tree synthesis (CTS), advanced routing, physical
synthesis-based optimization, chip finishing, path based analysis (PBA), signoff
quality analysis and ECO optimization. Super tight with PrimeTime. Claims recent
high profile ARM core PnR "win" that was 300 Mhz faster Fmax than CDNS Innovus.
Meditek, Intel, Samsung, AMD, Microsoft, Sony, ST, Renasas, ARM, Synaptics users.
Synopsys DSO.ai is Sassine's answer to Cadence Cerebrus with all of the
exact same AI claims but for his SNPS Fusion Compiler. Also has 350+ tapeouts.
Samsung, MediaTek, ARM, Renesas, ST, IBM, SK Hynix, Microsoft, Sony, Intel users.
(booth 2441) Ask for Jim Schultz. Freebee: pens & coffee
FPGA STUFF
11.) Blue Pearl Visual Verification lets FPGA engineers visually verify
with graphical FSMs, CDC, and false path viewers with cross probing to
RTL, with forward and reverse tracing, and linting message filtering.
They upgraded its simultaneous clock and clock domain analysis CDC stuff.
Reads and obfuscate encrypted IP to IEEE 1735. It lets encrypted IP to
be used during clock domain crossing analysis.
From last year -- Blue Pearl added reset domain crossing RDC. Also worked
they with NanoXplore SAS to design/test radiation hardened FPGA designs.
Microsoft, Lockheed, Bechtel, Raytheon, Thales, Navy Research Lab,
Harris, Ricoh, GE Medical, MBDA, BAE, Fujitsu, NEC, Bechtel, GE.
(booth 1439) Ask for Simon Matthews. Freebie: pens
Blue Pearl HDL Creator is an editor with 2000 real-time checks to fix
issues as you code, such as compilation and missing dependencies.
(booth 1439) Ask for Simon Matthews. Freebie: pens
Siemens Precision Synthesis does synthesis-based automated single event
effect mitigation methods such as triple modular redundancy (TMR),
fault-detect and fault-tolerant FSM encoding in FPGAs. ISO 26262,
DO-254, and IEC 61508. SEE mitigation in safety-critical designs.
LEC flow for datapath FPGA designs. Siemens Precision loosely rivals
Synopsys Synplify Premier. Customers "have small black helicopters."
(booth 2521) Ask for Rakesh Jain. Freebee: espresso & beer
Siemens Questa Equivalent Design FPGA does equivalence checking but for
FPGAs; sort of like Cadence Conformal, Synopsys Formality but for FPGAs.
It does RAM reduction, identical cell detection, instance mapping, etc.
on bigass FPGAs from Intel (Altera), AMD (Xilinx), and Microchip. Made
for Hi-Rel, A&D, Safety Critical, and Security on larger FPGA designs.
(booth 2521) Ask for Chris Giles. Freebee: espresso & beer
Siemens Questa PS adds PSS modeling to Questa Prime FPGA simulation
UVM verification flows. Does Breker Trek or CDNS Perspec in FPGAs.
(Booth 2521) Ask for Mark Olen. Freebie: espresso & beer
CALIBRE, STAR-RC, & RIVALS
12.) This is Joe Sawicki's legacy: to have the tool that defined DRC/LVS. It made 100's
of millions of $$$$ for Mentor in it's day. Some folks even used to describe Mentor
as "that company that owns Calibre DRC/LVS -- and a few other smaller EDA tools."
Siemens Calibre nmDRC is the industry's DRC king with 2nm tapeouts for sign-off and
they're developing 1nm. Scales to 2,000+ CPUs for designs and 10,000 CPUs for
manufacturing. Rivals are SNPS ICV & CDNS Pegasus. Lots of ML/AI to see -- and
lots cloud stuff at DAC with AWS and Azure. TSMC, Samsung, Intel, GlobalFoundries,
SMIC, UMC, and TowerJazz all use Calibre with in unimaginable numbers of licenses.
(booth 2521) Ask for John Ferguson. Freebee: espresso & beer
Synopsys IC Validator does DRC/LVS like Siemens Calibre. It has tight hooks in ICC2
and Fusion Compiler. Scales 2000+ CPUs. Claims "largest reticle limit chips with
billions of transistors" and "DRC, LVS, and dummy fill in same-day turnaround time."
It lets Fusion Compiler sign-off analysis and automatic repair. IC Validator PERC
uses Star-RC for R-extraction and Python for programming. That flow does netlist
checks, netlist driving layout DRC checks, P2P, and current density checks. SNPS ICV
is the big challenger to Siemens Calibre. Intel, Nvidia, Samsung, MediaTek, AMD.
(booth 2441) Ask for Srinivas Velivala. Freebie: pens & coffee
Cadence Pegasus "massively parallel DRC engine" runs "100's CPUs". Claims 8X/12X
faster than old MENT Calibre. For CDNS Innovus PnR, Pegasus does signoff DRC,
incremental DRCs, signoff metal fill, incremental metal fill, timing-aware metal
fill, and MPT decomposition for FinFETs. Over the years Sawicki had fun torturing
Anirudh about there being no TSMC certified runsets (ESNUG 576 #1, 585 #1); but
that changed April 2019 when TSMC put out certified Pegasus runsets for 7nm and
5nm. Now Pegasus has 2nm runsets. Will Mike Ellow now be losing sleep on this?
TI, Microchip, TSMC, Samsung, Global Foundries, Intel, and Microsemi are users.
(booth 1511) Ask for Bala Kasthuri. Freebie: lotto stamp
Siemens Calibre nmDRC Recon -- a blazing fast Calibre RealTime tool to quickly ID
systematic design issues during early iterations. Typical run times >10x faster than
standard Calibre nmDRC. Also, able to gray box (waiver) out known immature blocks
for even faster run times and to supress nuisance errors accelerating designer debut.
Used at all the IC Insight's top 25 companies. Cloud ready on AWS/Azure.
(booth 2521) Ask for Michael White. Freebee: espresso & beer
Siemens Calibre RealTime Digital does instant sign-off DRC checking and fixing
inside Innovus and ICC2/Fusion Compiler and Aprisa. Same deck, same engine and
same results as batch Calibre. Like CDNS Pegasus Interactive and SNPS ICV,
but it's 40% to 85% faster. ESNUG 584 #1. (booth 2521) Ask for Joe Davis.
Calibre Pattern Matching replaces text-based design rules with visual geometry
capture and compare. It did SRAM checking for TSMC 7/5/3/2nm. One-click symmetry
checking, one-click pattern identification, AI for Results Classification. 3nm use
in volume production, pilot at 2nm. Removes patterns that are "yield detractors."
Aimed at 7/5/3/2/1nm designs. Also it's key to Samsung's Closed Loop DFM for faster
yield ramps. Does AWS/Azure/GPC. TSMC, Samsung, GlobalFoundries, SMIC, UMC users.
(booth 2521) Ask for Michael White. Freebee: espresso & beer
Synopsys Star-RC is the gold standard for parasitic extraction. "5nm and below."
"Does hybrid extraction with AI-driven reference field solver for angstrom nodes."
"Billions of instances in one day and production proven for all multi-die designs."
Rivals are CDNS Quantus and MENT Calibre-xACT. Intel, Samsung, Broadcom, Qualcomm.
(booth 2441) Ask for Jim Schultz. Freebie: pens & coffee
Cadence Quantus QRC competes with Star-RCXT and Calibre-xACT. Does multi-corner
& statistical/inductance RLCK extraction, 16/14/10/7/5nm modeling, distributed
processing, netlist reduction, SNA. Double patterning, 3D-IC. Has 41 FinFET
customers and 3 FD-SOI. Reliability. Constraint validation. Works "in-design"
in Innovus and Virtuoso. Quantus QRC was in AWS and Azure clouds years ago.
(booth 1511) Ask for Hitendra Divecha. Freebie: lotto stamp
Siemens Calibre-xACT does massively parallel full chip RLC parasitic extraction
without tiling. Processes entire net on a dedicated CPU. No boundary nor halo
effects. "Attofarad accuracy with multi-million instance digital or custom
designs." Hybrid MOL/BEOL solver good to 3nm. Multi-patterning. Decks from TSMC,
Samsung, GF available. Tight links to Aprisa. Both field solver or table based.
(booth 2521) Ask for Carey Robertson. Freebee: espresso & beer
Lorentz PeakView does 3D EM extraction and modeling. Has vertical
inductance, multi-sheet extraction, and chip-package EM co-simulation.
Competes with Ansys HFSS. Users are Qualcomm, TI, TSMC, GF, Samsung.
(booth 1516) Ask for Henry Chi. Freebie: mugs
Sage iDRM is a physical design rule compiler. It finds all places
in your physical design where your "test" rule applies -- plus where
it's been violated. It helps make sensible DRC decks. 22nm - 2nm.
(booth 1522) Ask for Coby Zelnik. Freebie: pens
Siemens Calibre YieldEnhancer fills both low nodes and complex analog
blocks. Has push button ECO Fill solution. 3nm in volume production,
pilot at 2nm. Cloud AWS/Azure. Synopsys IC Validator and Cadence
Pegasus are competitors. TSMC, Samsung, IFS, GlobalFoundries, SMIC, UMC.
(booth 2521) Ask for Jeff Wilson. Freebee: espresso & beer
Siemens Calibre PERC does circuit reliability verification, and is in cell, block,
and full-chip 3rd party sign-off flows to check for common electrical failures such
as Electrostatic Discharge (ESD), Latch-Up, and Electrical Overstress (EOS). Has
extensions to Calibre YieldEnhancer for net-aware and orientation-aware metal fill.
New this year, ESD for 3DIC is a real PITA. We also do reliability for 2D plus 3DIC.
PERC support by TSMC, GF, Samsung, TowerJazz, UMC. Users Xilinx, Broadcom, ST, ARM.
(booth 2521) Ask for Carey Robertson. Freebie: espresso & beer
Ansys Helic Exalto does 3D electro-magnetic (EM) crosstalk analysis
and signoff. Has killer capacity/speed/accuracy. 12 Ghz chip with EM
coupling through PWR/GND. 2.8mm X 700u, with AP, M12-M7. Extracted
in 36 hours on 20 cores. Exalto is the only EM sign-off tool that
can handle designs with 2,000 ports doing full RLCK extraction in
40 hrs with 16 CPUs and 150GB of RAM. With 32 CPUs, under 1 day.
Exalto works with Star-RC, Quantus, Calibre-xACT. Huawei, Qualcomm.
(booth 1308) Ask Yorgos Koutsoyiannopoulos. Freebies: pens
Ansys Helic Pharos does EM risk-analysis. Analyzes EM isolation
between selected victim nets and all potential aggressors; does up to
100 billion pairs. Pharos does 2,000 ports vs. HFSS 30 ports. Gives
EM isolation "heat maps" with GHz frequency sweeps. Nothing like it
before. With Star-RC, Quantus QRC, Calibre-xACT. See ESNUG 584 #4.
(booth 1308) Ask Yorgos Koutsoyiannopoulos. Freebies: pens
Siemens Calibre DesignEnhancer is analysis driven Calibre-correct
physical design chip finisher for improved EM/IR robustness, design
quality and time to tape out. Competes with ICC2/Fusion and Innovus
chip finishing tools. Claims over 20 customers in production.
Public customers are ST Microelectroncs, Samsung, Juniper, Intel.
(booth 2521) Ask for Jeff Wilson. Freebee: espresso & beer
Silvaco (Infiniscale) TechModeler takes IV curves from silicon or 3D
parasitic extraction and uses a neural network to make very accurate
behavioral Verilog-A models from a small sample size that can be
simulated in SPICE. It competes with Keysight's NeuroFET.
(booth 1539) Ask Babak Taheri. Freebie: tape measure
Silvaco Belledonne compares layout versus layout, quickly finds the
differences with respect to wiring, and tells if diff is important.
Now 2x faster and can compare 5 different netlists at the same time.
(booth 1539) Ask for Babak Taheri. Freebie: tape measure
Silvaco SmartDRC & SmartLVS -- rivals Calibre, Pegasus, IC Validator
(booth 1539) Ask for Babak Taheri. Freebie: tape measure
Silvaco Viso is their new parasitic extraction viewer.
(booth 1539) Ask for Babak Taheri. Freebie: tape measure
MARGINs & ECOs
13.) Easy-Logic ECO Surgery does rewiring based functional ECO's. Surgery does both
pre-mask ECO and post-mask ECO. Logic patch generation, scan chain fixing, low power
cell insertion, and metal ECO "new ECO patches sized just 1/100 to 1/1000 of manual".
It won ICCAD CAD contest 3 years (2012, 2013, 2014). Runs in CDNS/SNPS/MENT flows
(booth 2430) Ask for Kager Tasi. Freebie: candies
Synopsys Tweaker is a family of physically-aware ECO tools:
Synopsys Tweaker-T1 vs. PrimeTime-ECO vs. Cadence Tempus-ECO
Synopsys Tweaker-F1 vs. Cadence Conformal ECO
Static/dynamic power ECO's. 50 M inst. 16/14/10/7/5nm FinFET. It supports
Intel/GF/Samsung/TSMC foundries. Does hierachical/timing/CPU/IR-drop ECO flows.
Samsung, Intel, AMD, NVIDIA, Google, Broadcom, Qualcomm, LG, TSMC, Mediatek, Xilinx.
(booth 2521) Ask for Bradley Geden. Freebee: pens
Empyrean XTop physical MCMM timing ECO tool. PBA timing fixes,
route-based timing fix. 16/14/10/7/3nm 100M inst. 5X faster. ClockExplorer
does CTS clock analysis and constraint generation. It helps cuts clock
insertion delay. Marvell and HiSilicon are XTop users.
(booth 2513) Ask for Jason Xing. Freebie: fluffy animal
Cadence Conformal ECO Designer generates "congestion-aware ECOs" for "last-minute
difficult ECO areas" for pre- and post-mask layout. Fast setup, 10X TAT and clever
scan chain preservation stuff. Broadcom, Qualcomm, ST, Samsung, Mediatek, AMD.
(booth 1511) Ask for Jayanth Prakash. Freebie: lotto stamp
Synopsys Formality ECO automates late-stage functional ECOs. Does targeted synthesis
to focus only on the regions of change between the original RTL. Then it equivalence
checks the tiny patch that meets timing. Samsung, Intel, AMD, NVIDIA, Google users.
(booth 2441) Ask for Avinash Palepu. Freebie: pens & coffee
DESIGN COMPILER & RIVALS
14.) Cadence Genus is an attack on Aart's 35 year Design Compiler franchise. It's
Anirudh's home-grown, massively parallel, RTL-and-physical synthesis tool that's
"5X faster" than Design Compiler and "1/2 iterations in block-level synthesis".
7 years ago, Genus got #4 "Best of 2017" with users in DAC'17 #4 and won a
user benchmark vs. DC-Graphical in ESNUG 582 #1. But that was 7 years ago.
Big selling point is it's tight with Cadence Innovus PnR, Tempus STA, and Joules.
Last year Genus added intelligent awareness of congestion in synthesis, and some neat
block-centic and datapath-centric optimizations. Genus has nothing really new to
say this year other than "Genus has AI everywhere and is on AWS/Azure/GCP cloud!"
Broadcom, Texas Instruments, Cienna, MaxLinear, Cisco, ImgTec are users.
(booth 1511) Ask for Hitendra Divecha. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
Synopsys Design Compiler NXT is now 2x faster than Design Compiler Topo. "We beat
Genus in benchmarks!" Improved correlation with ICC2 and Fusion Compiler at 5/3/2nm.
DC is the most widely used synthesis tool with 600 logos and 35+ years in the market.
(booth 2456) Ask for Jim Schultz. Freebee: pens
RISC-V vs. ARM
15.) Codasip Studio creates application specific processors starting from
their production RISC-V IP. It generates RTL, UVM, and the software
design kit (compiler, debugger, profiler, ISS, etc.) from a single
high-level language. It competes against Synopsys ASIP Designer, ARM,
SiFive, and Andes. Codasip Studio 9.4.2 has better RTL performance
and area this year. The demo shows 91% reduction in runtime and energy
consumption with a 39% area increase. Also shows design exploration
to find interesting points for specific needs. (FYI -- Axel Strotbek,
the former CFO of Audi has now joined the Codasip BoD.) Users are Mythic,
Trinamic, Silicon Arts, Analogix, Xinsheng/Dahua, Dongwoon Anatech.
(Booth 1536) Ask for Troy Jones. Freebie: pens
Breker RISC-V Core and SoC Test Generator SystemVIP automatically
generates RISC-V tests for platform issues - e.g. Coherency, Security,
Load Store, Interrupt, etc. Competes against Google RISCV-DV Instruction
Generator. IBM, Broadcom, AMD, Sanechips (ZTE), ADI use Breker instead.
(Booth 2447) Ask for Adnan Hamid. Freebie: SF candy
Synopsys Imperas ImperasDV does timing driven RISC-V custom instruction design and
optimization. Added configurable SystemVerilog functional coverage model
called riscvISACOV. "Save months of engineering effort with our lock-step
asynchronous continuous compare flow." NSI-TEXE, Marvell, Dolphin Design,
Ventana, Lightelligence, Nvidia Networking (Mellanox), OpenHW Group,
Silicon Labs, NXP, Intrinsix, lowRISC, Seagate are all Imperas users.
(booth 2441) Ask for Larry Lapides. Freebie: pens
Mirabilis VisualSim RISC-V Architect does micro-architecture system modeling
that models your RISC-V pipeline at 98% functional and timing accuracy without the
use of RTL or emulation. It can execute benchmark code and provide detailed
statistics of the instruction, pipeline, execution, TLB, Cache, memory, and
peripherals. VisualSim gets cycles per instruction of 0.59 in the simulation
vs 0.56 in the actual Silicon. This block can execute the Dhrystone, Radar, or
network protocol code in cycle-accurate detail. The user can easily
modify the openly available code to import their design customization.
RISC-V core statistics, debugging, traces, power, and timing reports.
Qualcomm, AMD, Western Digital, Denso, Northrop Grumman, Lockheed, NASA
(booth 2342) Ask for Deepak Shankar. Freebie: Indian candy
RTL & GATE POWER
16.) Cadence Joules is an RTL power cutter. Estimates power at RTL to within 15% of
signoff power. It has "power scrubbers". Joules works with Genus and Palladium.
Guided RTL cuts power up to 25%. RTL stimulus for activity-driven power reduction.
Joules xReplay works with Xcelium to power reclaim and glitch power analysis using
RTL vectors. "Now with lots of AI and AWS/Azure/GCP cloud everywhere!" Users
are Qualcomm, Maxlinear, ARM, Broadcom, TI, Socionext, Renesas, Microsemi, ADI
(booth 1511) Ask for Jeff Roane. Freebie: lotto stamp
CDNS Jasper Low Power App formally verifies lower power designs that
have multiple voltage and power-management domains. Checks to see if there are
any issues that pop up after the insertion of power management circuitry.
(booth 1511) Ask Pete Hardee. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
Synopsys PrimePower does gate-level power analysis reports. Synopsys RTL Architect
does predictive RTL-level power estimation. PrimePower does average power, peak
power, glitch power, clock network power, dynamic & leakage power, and multi-voltage
power; with activity from RTL and gate-level vectors, and vector-less analysis.
MediaTek, Google, Intel, Broadcom users. (booth 2441) Ask for William Ruby.
Synopsys Spyglass Power users got 9% to 16% power cut on Verilog RTL.
RTL, gate-level, or post-layout. FSDB, VCD, SAIF and vectorless. Does ECO's, CPF,
UPF, mem in sleep mode. ERC checks on P/G netlist. Power modeling & clock gating.
(booth 2456) Ask for Jim Schultz. Freebee: pens
---- ---- ---- ---- ---- ---- ---- ---- ----
Siemens PowerPro Optimizer does RTL power optimization. Users see 9% to 12% general
Verilog RTL power savings. 37% cut in sequential logic power saving in ESNUG 535 #2.
Chatting up their "What If" ability with to quickly understand power effects of
potential mode, operating environment or design changes "saving hours of turn-
around-time". PowerPro is only tool tight with Questa SLEC, which sequentially
verifies if your low power RTL tweaks equals your original RTL. New static checks
portfolio. Rivals Ansys PowerArtist, Synopsys SpyGlass Low Power, and Cadence
Joules. Gets ~85% correlation to gate-level. 7/5/3nm FinFET. Qualcomm, TI,
Samsung, ARM, Raytheon, Google, NXP are users.
Siemens PowerPro Estimator does RTL power analysis on billion gate SoCs with million
cycles of SW-driven workloads enabled. Partitioning flow, multi-CPU framework.
(booth 2521) Ask for Fahad Mohammad or Quazi Ahmed. Freebie: espresso
---- ---- ---- ---- ---- ---- ---- ---- ----
Apache PowerArtist users saw 3% to 10% reductions. Does automatic and guided.
Sequential and combinational clock-gating constructs, memory light/deep sleep modes,
and wasted power in datapath logic. RTL power accuracy within 15% of sign-off.
10 M gates in 1 hour. 10/7/5/3/2nm. Handles 100M+ instances. Hooks with RedHawk-SC
for power grid integrity. Also peak power & thermal hotspot analysis. Tight hooks
into Siemens Veloce emulation and its Power App. Activity streaming 10X faster vs.
old slow FSDB for millisecs of activity. Broadcom, Nvidia, Samsung, ST, NXP, ARM.
(booth 1308) Ask for John Lee. Freebie: stuffed animal
Baum PowerBaum does static & dynamic RTL power analysis that's up to
"100X to 200X faster" vs. PowerPro/PowerArtist/Spyglass. "We couldn't
find a fast/accurate tool to do this, so we built one of our own!"
(booth 1311) Ask for Andy Ladd. Freebie: none
Mirabilis VisualSim Power v2.0 measures system level power on
your SoC or uP model. Does power gating and sleep modes. Users
are China Auto, IBM, Analog Devices, AMD, and Sandia Labs
(booth 2342) Ask for Deepak Shankar. Freebie: Indian candy
RTL ENVIRONMENTS & RTL SIMULATION TOOLS
17.) Cadence Verisium (formerly Cadence Indago) is Anirudh's answer to Sassine's
SpringSoft Verdi3 empire. Verisium Debug works by adding Big Data Capture to Root
Cause Analysis plus "more AI stuff" -- to data mine your CDNS tool run logs -- to
"highlight causality" and correlations causing your bug in the first place. Does
HW/SW bug hunting. Verisium Manager (the AI version of CDNS vManager does
regression optimization, failure triage, verification planning & coverage closure)
was reported by DeepChip users to save "1hr/day/engineer" (See DAC'20 #2a).
Verisium Apps including SemanticDiff, PinDown, WaveMiner, and AutoTriage uses AI
to cut total debug time by 6-10x. "We got lots of AI, AI, AI everywhere now!"
Nvidia, Samsung, MediaTek, Analog Devices, TI, Bosch, Broadcom, Renesas, ST.
(booth 1511) Ask for Pete Hardee. Freebie: lotto stamp
Synopsys Verdi is the wildly popular design debug waveform viewer with a Qt-based
GUI. Aart got it with SpringSoft. Man, it does everything! UVM, OVM, System
Verilog, VHDL, SVTB, VMM, SVA, CDC, FSBD, UPF/CPF, nWave, nSchema and TFV, PDML,
CTS, SDC, STA, HW/SW. Used for 25+ years, Verdi now has AI cut debug time. It is
tight with the Synopsys simulation, emulation, formal, static, timing tools; and
includes a refreshed UI, innovative views, and correlation with transactions
and software. It's extensible and open architecture, based on the de-facto FSDB,
allows users, EDA partners and customers to further extend its capabilities.
New this year, Verdi has ML-binning of log messages, and the root cause analysis
engines reduce bug-finding by 60X. Intel, Microsoft, AMD, Qualcomm, Nvidia users.
(booth 2456) Ask for Bradley Geden. Freebee: pens
Cadence PinDown auto debugs regression failures by IDing the commits that cause the
test failures and automatically assigns bug reports to the engineers who made these
commits. PinDown debugs down to the exact line of code. It instantly detects
high-risk code changes without any simulation. Samsung, Broadcom, Synopsys users.
(booth 1511) Ask for Daniel Hansson. Freebie: lotto stamp
Defacto Star Design tools is an 8-part unified RTL design flow where
coherency between Verilog/VHDL RTL, SDC, IP-XACT, UPF, and SystemC
is guaranteed. Builder does RTL design editing and exploration.
Checker does simulation-free connectivity checks. Low Power does
UPF design exploration. Other parts do padring, DFT, IP, etc. See
review in ESNUG 530 #2. Users Qualcomm, Broadcom, Intel, Maxim-IC.
(booth 1528) Ask for Chouki Aktouf. Freebie: candy
Amiq Eclipse DVT IDE is an add-on to VCS/Questa/Incisive that lets
an engineer NOT have to continuously switch between his editor and the
"e"/SystemVerilog/VHDL simulator. IDE is sorta like Visual C stuff.
Samsung, Intel, Broadcom, Qualcomm, Toshiba, SK Hynix, Micron users.
(booth 1410) Ask for Cristian Amitroaie. Freebie: chocolates
Sigasi Studio is much like Amiq DVT. System Verilog & VHDL support.
In 2019, added Visual respresentation and GUIs for documentation.
NXP, UTC, ASML, Thales Group, Thales Alenia Space, Airbus, Philips,
Rohde & Schwarz, Bosch, Siemens, Facebook, MacLaren, Easics, Harris,
Prodrive, Johnson & Johnson, SCD, ABB, Saab, BAE, EPSON, GE, Dolby
Laboratories, CERN, Fraunhofer Institute, Heidenhain uses it.
(booth 2416) Ask for Bart Brosens. Freebie: Belgian chocolates
Sigasi Studio Veresta is a fast linter for CI/CD (analyzes Google
OpenTitan in 27 seconds on an Intel 12700K). Brings Sigasi Studio to the
command line, syntax checking, lints semantic checks, and style checking.
Works with SonarQube, Jenkins, Gitlab CI/CD, Github actions, etc. Give
overview on code quality. Cuts CI/CD costs by gatekeepering broken code.
(booth 2416) Ask for Bart Brosens. Freebie: Belgian chocolates
Agnisys DVinsight is a friendly editor for UVM developement sort of
like Amiq. Helps your write code. And their IDesignSpec converts
specifications for registers/sequences into UVM/RTL. Amazon, Google,
Marvell, OnSemi, Rambus, Conexant, Wipro, Conexant, John Deere, CERN
(booth 2457) Ask for Freddy Nunez. Freebie: travel mug
SystemC/C/C++/TLM STUFF
18.) Cadence Stratus HLS takes in untimed SystemC/C/C++ to generate Verilog RTL that
SNPS Design Compiler or CDNS Genus can easily digest. Can do both control logic
and datapaths. Claims better accuracy than Catapult. Hooks into CDNS Genus RTL
synth, Joules low power, and Innovus PnR. Supposedly can see PnR congestion issues
in your SystemC/C/C++ source. Socionext, Qualcomm, Syntiant, Raytheon, NXP, Bosch,
Samsung, LG, Realtek, Toshiba, Fujitsu, Ricoh all use Cadence Stratus HLS.
(booth 1511) Ask for Jeff Roane. Freebie: lotto stamp
Siemens Catapult HLS synthesizes C++/SystemC/MatchLib into
Verilog/VHDL to target either FPGA or ASIC. Does top-down and bottom up,
cuts project times 50% and verification costs by 80%. C->RTL visualizer.
Has libs and I/O for Xilinx and Altera to crank clock freq, has hooks
into Siemens Oasys-RTL. Partnership with Synopsys for better correlation
and QoR. Toolkits for AI/Machine Learning (YOLO Tiny) and complicated
math. AC_data_types open source on GitHub and still way faster than
SystemC types with no ambiguities. It's the King of HLS/HLV. Rivals
Cadence Stratus, Xilinx Vivado HLS. Nvidia, Google, ST, Meta, Alibaba.
(booth 2521) Ask for Stuart Clubb. Freebee: espresso & beer
Siemens Catapult Coverage does formal/lint checks on synthesizable
SystemC and C++ to prevent ambiguous or bad logic mistakes. Coverage
covers C statement, branch, toggle, expression, and array indexing; all
done hundreds of times faster than RTL simulation coverage. Qualcomm,
Nvidia, ST, Google, FotoNation, SeeCubic, Bosch, Fujitsu, Toshiba.
(booth 2521) Ask for Stuart Clubb. Freebee: espresso & beer
Siemens SLEC does SystemC/C++/C-to-RTL functional equivalence. Tight
EC with Catapult; less tight vs. SNPS Synphony or CDNS Stratus. Also
C++ assertion/property checks. Rivals Synopsys Hector and Jasper EC.
Runs "bottom up" partitions. LSF support. Nvidia, Google, ARM users
(booth 2521) Ask for Stuart Clubb. Freebie: expresso & beer
Siemens Catapult Formal are formal verification apps for coverage,
equivalency, and RTL assurance in the Catapult HLS flow. Unique to
the Catapult ecosystem. (booth 2521) Ask for Stuart Clubb.
Synopsys Imperas does virtual platform based software development, debug and test.
Acceleration on multicore hosts. It competes against Cadence Virtual, Synopsys
Virtualizer, Mentor Vista, and Wind River Simics. NoCs. Fault injection. Linux,
FreeRTOS, OpenRTOS, uC/OS, MQX, eCoS. Imperas OVP has 40 EPKs, 170 CPU models of
ARM, MIPS, RISC-V. Users ImgTec, Renesas, Recore, Altera, Audi, AMD, Nagravision.
(booth 2441) Ask for Larry Lapides. Freebie: USB charger
Synopsys Synphony HLS plays here but probably not showing at this DAC.
VERIFICATION IP
19.) Siemens Questa Verification IP (VIP) is a big ass library of UVM VIP.
- AMBA Family (CHI 5, ACE 4, ACE-Lite, AXI4, AXI3, AHB, APB);
PCIe Family (PCIE 4.0, PCIe 3.0, PCIe 2.0, PCIe 1.1, PIPE, PIE-8,
SR-IOV, MR-IOV, NVMe, AHCI); USB Family (USB 3.1, USB 3.0+OTG,
USB PD, PIPE, xHCI, SSIC, USB 2.0+OTG, UTMI+, UTMI, ULPI, oHCI,
eHCI); Ethernet (400G, 100G, 50G, 40G, 25G, 10G, 1G, 100M, 10M,
PTP, MDIO, EEE, MII, RMII, GMII, TBI, RTBI, SGMII, RGMII, QSGMII,
BASE-X, BASE-T, BASE-R, BASE-W, CAUI, XGMII, XAUI, XLAUI, RXAUI,
HI-MoM, XSBI, XLGMII, CGMII, HiGig2, FEC, Auto-Neg); Serial Family
(SmartCard, SPI-TI, SPI-Moto, SPI-NS, SPI 4.2, UART, I3C, I2C 5.0,
I2S-Philips, I2S-TI, JTAG); MIPI Family (MPHY 3.0, LLI 2.0,
DSI 1.1, CSI-3, CSI-2, DigRFv4 1.2, HSI 1.0.1, Unipro 1.6,
UFS 2.0); DDR Family (LPDDR4, LPDDR3, LPDDR2, DDR4, DDR3, DDR2,
DFI 3.1, Wide IO 2, DRAM Model Generator); FLASH Family (SDCard4.2,
SDIO4.1, eMMc5.1, ONFI4.0, Toggle, UFS, Parallel NOR, Serial NOR);
Display (CDC, DisplayPort, eDP, V-by-One, HDMI 2.1, HDMI 2.0,
HDMI 1.4, HDCP 1.4); HyperBus (Hyperram, Hyperflash); Auto (CAN,
CAN-FD, LIN); Mil-Aero (Spacewire, 1553b, PCI); 5G (JESD204B,
CPRI); Storage Family (SATA); NVMe over Fabric, Interlaken, I3C.
Now added PCIe 5, USB 3.2, DDR 5, LPDDR 5, UXSGMII, Ethernet Base T
Each protocol comes with a testplan, functional coverage, assertions,
examples and stimulus. ARM, Cypress, Microsemi, Marvell, ST users.
"Oh, don't forget we have 1700 combinations of memory models, too!"
(booth 2521) Ask for Gordon Allen. Freebee: espresso & beer
Siemens Avery IP (VIP) does PCIe 5.0, DDR5, HBM2E, CXL, CCIX,
Gen-Z, Ethernet 400G, CSI/DSI, I3C; ARM and RISC-V. "Use all 59 VIPs
with one license." UCIe this year! Samsung, Broadcom, Xilinx, Marvell.
(booth 2521) Ask for Gordon Allen. Freebee: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
- have VIP for "AMBA 5 CHI-e, AXI, ACE, eMMC 5.0, HDMI 2.1, GDDR6/7, DDR5,
LPDDR5, MIPI C-PHY, 2, MIPI SoundWire, PCI Express Gen 4/5/6, CXL 2/3,
TileLink, UART, SPI, I3C, USB 3/4, Ethernet 25G/50G/100G/400G/800G,
HBM 2/3, HMC, MIPI CSI-2, MIPI DSI-2.
- Recently added UCIe, PCIe 7, HBM4, USB-4, Ethernet 1600G, SWI3S
Denali-style API, all simulated VIP runs on VCS, Questa and Xcelium.
"VCS or Questa customers do not need Specman e". TripleCheck. "CDNS VIP
runs 2x faster vs. SNPS VIP due to optimized VIP C cores!" Broadcom, HP,
IBM, Intel, LSI, Hitachi, Marvell, Qualcomm, Samsung all use CDNS VIP.
(booth 1511) Ask for Boyd Phelps. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
SmartDV SmartCompiler lets users customize any of the 700+ SmartDV
standards-based design IP and VIP products in the SmartDV catalog.
It uses a proprietary high-level language input to automate creating
and/or customizing of IP -- and spits it out in the user's desired
methodology. The resulting "IP Your Way" is higher quality and more
cost-effective than manual customization, with 10x less engineering
effort. "We've been using SmartCompiler for 16 years to generate
literally all of our own IP. We've customized 100's of IP cores."
(booth 2429) Ask for Mohith Haridoss. Freebie: Starbucks gift card
PORTABLE STIMULUS
20.) Portable Stimulus (PSS) promises UVM reuse from HW all the way to SW.
UVM Simulation ==> HW/SW Emulation ==> final post-Silicon
For a good detailed tech primer on PSS, see ESNUG 578 #1, #2, #3.
Breker TrekSoC had slipped behind CDNS Perspec in "Best of 2018". (DAC'18 #2b)
But I still recommend seeing Breker at DAC'24 because you can easily see Perspec at
all the CDNlive events. In 2019, Breker added DSL input, and better synthesis to
UVM. Then in 2023 "we extended it to handle complex SoC verification requirements,
firmware, processor cores." Breker's strength is it's output is easy to make into
testbenches. Broadcom, Nvidia, Intel, ADI, AMD, ZTE are all Breker users.
(booth 2447) Ask for Adnan Hamid. Freebie: SF candy
Cadence Perspec is the not-C++ but DSL side. It's a multi-core ARM/RISC-V verification
library/tool for cache coherency, distributed virtual memory, low power. "We're
swimming in ARM and RISC-V cores, John!!! Swimming!" Five years ago, Cadence Perspec
was voted #2 overall by users as "Best of 2018". (See DAC'18 #2a). Qualcomm, AMD,
Analog Devices, Samsung, Mediatek, Renesas, ST, TI, and Infineon use Perspec.
(booth 1511) Ask for Pete Hardee. Freebie: lotto stamp
Siemens Questa PSS adds PSS modeling to UVM flows. Complements Cadence Perspec
and Breker Trek. Works with Questa in real time. View PSS scenarios even before
running simulations. You can view PSS scenarios even before running simulations.
(booth 2521) Ask for Tom Fitzpatrick. Freebie: espresso
Synopsys still isn't showing a PSS tool at DAC'24. Rumor was years ago they were
looking at acquiring Breker to fill that hole; but that didn't happen.
HARD & SOFT IP
21.) Synopsys is showing its Virage DW ARC 600 & 700 cores, plus its mem IP, plus std
cell libs; that all directly compete against ARM. DW ARC HS4x and HS4xD processors.
6000 DMIPS per core. Security. ARC now has 226 customers. DW ARC comes in low
power and audio. "Hey! You engineers! STOP looking at those damn RISC-V cores!"
(booth 2441) Ask for Joachim Kunkel. Freebee: pens
Cadence IP Portfolio has interface IP for USB, PCIe, MIPI, Ethernet; analog
mixed-signal IP for 224G/112G/56G SerDes, ADC, DAC, AFE, power mgmt; peripheral IP
for I2C, I2S, PWM; Denali memory IP for HBM 4/3, GDDR 7/6, DDR/LPDDR, 5X/5/4 with
up to 9600 Mbps WideI/O, NAND Flash; Tensilica for baseband, audio, imaging/video.
PCIe 7/6/5 with CXL and IDE, UCIe 32G AP/SP. New this year -- they have chiplet
IP for automotive with ARM. (booth 1511) Ask Boyd Phelps. Freebie: lotto stamp
Silvaco Samsung Foundry IP -- holy crap! How did Iliya's little tiny
company manage to get the rights to sell Samsung Foundry design IP for
their 14nm, 11nm, 10nm, 8nm FinFet and 28nm FD-SOI process nodes???
PCIe, DDR/LPDDR, MIPI PHY, Ethernet, HDMI, USB3.1, DisplayPort,
V-by-One; along with data converters, PLLs and other analog IP.
(booth 1539) Ask Babak Taheri. Freebie: tape measure
Silvaco Xena scans a chip-level database to list all detected IP and
versions of that IP. Works for embedded SW, too. It scores the
extent to which IP exists in the chip, from its entirety to fragments.
(booth 1539) Ask Babak Taheri. Freebie: tape measure
Silvaco NanGate IoT Std Cell Libs are "IoT optimized" full custom
libraries. 9000 cells, 5 VTs, 3 gate lengths. 28/40/65/90nm si proven.
Cut area 8-14%. "Our 8T 28nm GF lib got 55% higher raw gate density."
(booth 1539) Ask Babak Taheri. Freebie: tape measure
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precision clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 1342) Ask for Mahesh Tirupattur. Freebie: none
CAST has a mess of 8051 cores, GPU and accelerator IP cores, CAN FD,
H.264 encoders, JPEG IP. Geon "secure" uP, J2716, MIL-STD 1553.
(booth 2411) Ask Nikos Zervas. Freebie: stylus pen
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". Now multiple proven 7nm PLLs this year.
"We have 5nm PLLs, too!" TSMC, SMIC, UMC, GF, Samsung, ARM, Toshiba
(booth 2225) Ask for Andrew Cole. Freebie: USB car chargers
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180nm to 7FF+. (booth 1337) As for John Maneatis.
TEST/SCAN/BIST/JTAG/FAULTS/DFT
22.) Here's why Mike Ellow's test brainiacs are crushing Sassine & Anirudh in test.
Siemens Streaming Scan Network (SSN) drives packetized scan data
(100% payload, no address data) to your chiplet/multi-die design. Cuts
test time 80%. Scalable. "Your core DFT planning is decoupled from your
chip, thus boosting your TAT". Can do plug-and-play last-minute design
changes without affecting DFT architecture. Cuts your power profile by
reducing IR-drop -- meaning passing more margins on your first silicon.
Tests identical cores with on-chip compare. Well-designed clock timing
for fast silicon bring-up. Supports hierarchical and tiled designs.
Supports burn-in and scan chain failure analysis through laser voltage
probing/imaging (LVP/LVI). Intel, Amazon, Broadcom, Qualcomm, Samsung.
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
Siemens Tessent Diagnosis localizes silicon manufacturing defects by
analyzing failing test cycles from the ATE using design data and with
Tessent TestKompress ATPG patterns. Diagnosis data is routinely used to
guide failure analysis and volume diagnosis to improve yield. Competes
with Synopsys TestMax Diagnosis. New this year, LVI/LVP guided by chain
diagnosis making it even easier for designs containing SSN. Encrypted
design collateral can be shared by the fabless to enable foundries to
run diagnosis. (This encrypted flow changes all the names in a design
including pin names, instances and blocks to a garbled string that lets
the foundry to run diagnosis, while simultaneously protecting the IP of
the fabless so bare design names are no longer visible.) It also has a
SSN on-chip-compare so multiple identical cores to be tested all together
saving a tone of test time. Qualcomm, TSMC, Microsoft, Samsung, Cypress
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
Siemens TestKompress does hierarchical ATPG. Patterns are generated
independently for each core. Can be retargeted at chip top-level.
10x faster generate time and 1/10th CPU time of Synopsys TetraMAX.
Pattern count is 1/2, so less test time. Also this core-level ATPG
means no wait for whole design to be done before ATPG generation.
TestKompress does end-to-end hierarchical, which takes DFT out
of the critical path, reduces ATPG and diagnosis runtime by 10X,
and pattern count by another 2X. Users are Broadcom, NXP, Renesas,
OnSemi, Intel, NXP, Mediatek, Spreadtrum, and Annapurna Labs.
(booth 2521) Ask for Geir Eide. Freebie: espresso & beer
Siemens Tessent MissionMode does hardware functional safety stuff by
system-level low latency access to on-chip test resources for on-
line test and diagnosis. Non-destrictive memory tests, too. Works
with Tessent LogicBIST and MemoryBIST or other IJTAG test IP.
Siemens Tessent ScanPro places test points in netlist for compression.
Adding 1%-2% area for a 3X to 4X reduction in ATPG test patterns.
If 100X compression with Synopsys TestKompress, Mentor ScanPro gets
300X to 400X. VersaPoints for hybrid ATPG/BIST coverage. OCC
insertion, X-bounding for logic BIST. Improves logic BIST coverage
by 2%-4% and gets to 90% coverage 8x faster. ISO 26262 likes this.
(booth 2521) Ask for Geir Eide. Freebie: espresso & beer.
Siemens Tessent IJTAG lets IEEE 1687 compliant blocks be hierarchically
scan accessable. Automatic ICL design and PDL retargeting at any design
level. New this year -- you can run IJTAG faster using TCK clock
stretching as well as ICL visualization and faster debug capabilities.
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
Siemens Tessent RISC-V Trace Encoder does post-silicon debug and software
dev on RISC-V designs by monitoring program execution in real time. It
encodes program execution (instruction trace) and the data from "load and
store" instructions (data trace), outputting trace in compressed format.
It's a cycle-accurate trace so the user can optimize software performance.
Competes with SiFive Insight. Seagate uses our Tessent RISC-V traces.
(booth 2521) Ask for Geir Eide. Freebie: espresso & beer.
Siemens Tessent Embedded Analytics is a bucket of IP, embedded, and host-
run software and software development kits to "slash SoC validation cost,
provide system-wide real-time debug, and post-deployment analytics based
on functional monitoring." Competes with Synopsys SiliconMAX. Showing
a new powerful software stack letting users develop/debug/monitoring
applications running either embedded on the SoC, or on a separate host.
(booth 2521) Ask for Geir Eide. Freebie: espresso & beer.
Siemens Tessent LogicBIST-OST software improves BIST coverage and
reduces time-to-coverage for ISO 26262 by inserting patented Observation
Scan Technology (OST) test points. These points are observed every shift
cycle meaning less patterns are needed. Renesas, Intel, Microchip.
(booth 2521) Ask for Lee Harrison. Freebee: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
Synopsys TestMAX DFT because of tight hooks with Design Compiler, TestMAX DFT
stitches (and architects) scan chains to all the flip-flops in your chip, then
TestMAX ATPG generates ATPG vectors for those scan chains. It does clever
tweaks to be power friendly. Competes with Siemens Tessent and Cadence Modus.
Since Design Compiler has 600 logos, I suspect TestMAX DFT has 70% of them.
(booth 2441) Ask for Sri Ganta. Freebie: pens & coffee
Cadence Modus Test does scan insertion, compression, ATPG, logic and memory BIST.
Physically aware 2D elastic compression cuts test logic wirelength by 2.6X. Has
compression ratios 400X. Takes 1/3rd tester time. Works with Genus RTL synthesis
and because of hooks into Innovus/Genus it has lower routing congestion, fast
yield ramp. Texas Instruments, GlobalFoundries, Microsemi, Sequans users.
(booth 1511) Ask for Jeff Roane. Freebie: lotto stamp
Real Intent Meridian DFT is multi-test-mode static analysis to do
"shift-left" using specialized, fine-grained rules for early detection of
DFT issues. Rivals SpyGlass DFT/TestMax Advisor, Siemens Tessent ScanPro.
It checks multiple sets of rules in a single run, reducing setup time,
speeding up runtime, and accelerating debug. Does several million gates
in minutes with low peak memory footprint. Low noise, and ha fine rule
granularity to cut noise speed up debug and root cause analysis.
Fast setup, "takes only hours vs weeks for other DFT static tools."
FYI -- This is Real Intent's 25 year in business! Congrats Prakash!!!
(booth 2625) Ask for Kanad Chakraborty. Freebie: LED pens
Real Intent SafeConnect does connectivity and glitch detection on
early RTL and netlist level designs. Competes against SNPS Connectivity
Check and CDNS Connectivity Verification. Native command execution for
10X better runtime. Configuration commands for flexible, compact
specification. Options to control reporting and noise reduction. UPF
for design power intent analysis. Shows signal connectivity. Has a
library of pre-defined checks. Tight debug with annotated schematics
(booth 2625) Ask for Sanjay Thatte. Freebie: LED pens
Synopsys SpyGlass DFT does "RTL analysis for stuck-at/at-speed
testablity, low power design, JTAG/IEEE1500" and "RTL fault coverage
estimation for stuck-at, transition and random-resistive faults."
(booth 2456) Ask Ravi Subramanian. Freebie: pens
ROLL-YOUR-OWN EDA SOFTWARE STUFF
23.) Verific sells System Verilog, VHDL, UPF parsers with C++ interfaces
to EDA developers. Perl and python APIs. Synopsys, Cadence,
Mentor, Ansys, Xilinx, Altera, AMD, Nvidia, Infineon, Samsung,
AMD users. Has Invio, a collection of high-level Python APIs that
make it easier to interface with their core Verific parsers.
(booth 1414) Ask for Michiel Ligthart. Freebie: stuffed giraffe
Mirabilis Collaborator generates docs and javascript for executing
models within a web browser. Used as specification or a customer
demonstration tool. Does parameter/algorithmic/topology changes.
(booth 2342) Ask for Deepak Shankar. Freebie: Indian candy
Mirabilis VisualSim MBSE SoC Designer lets you import your SysML
to use Model Based Systems Engineering (MBSE) as the front-end for your
design process. VisualSim maps the behavior to a hardware platform, runs
simulation to estimate runtime and power of the proposed system. There
is no emulator, RTL or software code required for this process. It is
done using a virtual simulation model. Cuts development costs by 40%.
Northrop Grumman, Sandia National Labs, Shenzhen ICC, and Denso.
(booth 2242) Ask for Deepak Shankar. Freebie: Indian candy
WORKSPACE, DESIGN DATA MANAGMENT, & IP TOOLS
24.) IC Manage Holodeck bursts your on-prem chips and EDA tool flow into the
AWS/Azure/GCP cloud. It does intelligent data cheery-picking and only
uploads what the EDA needs on demand. With Holodeck, Xilinx got a 99%
faster 1st EDA tool launch, 99% smaller cloud footprint, used 41% less
CPU time in the cloud. Demoing VCS, RedHawk-SC, Virtuoso, Calibre
Dean on IC Manage Holodeck hybrid/native cloud speedup & less storage
IC Manage GDP design & IP data management system lets digital/custom
designers find, modify, release & track design data through tapeout.
Bug interdependency management. Multi-tier web stuff. Samsung, AMD,
Intel, Xilinx, Nvidia, Nokia, Northrop Grumman, Viasat, Aquantia.
IC Manage GDP-XL adds the following features to GDP: Customizable
schemas by project or component, with easily extendable templates.
Supports central, distributed & hybrid development. Web UI, REST API.
AMD, Nvidia, Samsung, Infineon, NXP, Microsoft, Qualcomm, Microchip, Rios
(booth 2317) Ask for Shiv Sikand. Freebie: Ghirardelli chocolates
IC Manage PeerCache for "hybrid cloud bursting & HPC cloud apps". Run
existing jobs in cloud in minutes, with minimum cloud storage costs.
PeerCache dynamically determines exact data needed by a job for fast
upload, with no data duplication or synch needed. ESNUG 582 #8. Also
supports pure cloud apps. Delivers scale out I/O. On-prem & cloud
infrastructure-compatible. Got top 5 "Best of 2017". (DAC'17 #5)
(booth 2317) Ask for Shiv Sikand. Freebie: Ghirardelli chocolates
IC Manage IP Central makes all a company's IP to be searchable and accessible to
every single design team to use. Google-like UI with filtering, then automatically
view and generate a datasheet. IP Central supports all DM systems and Git.
What's new: IP Central scales to 100M+ IP objects. Time machine feature gives
you full traceability & recovery of every database operation -- you literally
have version control of your db operations. NXP, Samsung, and Viasat users.
(booth 2317) Ask for Shiv Sikand. Freebie: Ghirardelli chocolates
IC Manage Envision competes with Cadence vManager but claims it's 10X-100X faster.
Uses big data algorithms for customized visual analytics and interactive reports
across mixed vendors. New: Jira integration of verification failure signatures.
(booth 2317) Ask for Shiv Sikand. Freebie: Ghirardelli chocolates
---- ---- ---- ---- ---- ---- ---- ---- ----
Cadence vManager is just like Questa VRM, but has an API bug systems,
source systems, or agile development systems. Very verificationy.
Deep hooks with Cadence Incisive, Palladium, Xcelium, and JasperGold.
Fujitsu, Analog Devices, ST, Qualcomm, Allegro, Infineon, Teradyne.
"vManager now has lots of AI and is on AWS/Azure/GPC clouds now, too!"
(booth 1511) Ask for Pete Hardee. Freebie: lotto stamp
---- ---- ---- ---- ---- ---- ---- ---- ----
Siemens Questa VRM is verification run management system that combines
coverage metrics from formal, CDC, simulation, and emulation engines.
Accellera UCIS standard, and Jenkins regressions. Competes with Cadence
vManager and Synopsys Execution Manager. Now swimming with AI/ML stuff
everywhere; plus Questa VRM does AWS/Azure/GCP. Nokia, Micron users.
(Booth 2521) Ask for Mark Olen. Freebie: espresso & beer
Siemens Solido CrossCheck (formly from Fractal) is a weird all knowing, all
seeing IP checker. It literally compares IP that's in 33 different formats
(Verilog, VHDL, .lib, LEF, DEF, GDS, schematics, etc.) to see how equivalent
they are. Sooooooo I can cross check my Verilog RTL to my GDS2 version
of a block to see if they're equal?
Here's the backstory to how CrossCheck ended up in Sawicki's hands:
How Amit & Ravi staged a (tiny) Pearl Harbor on Anirudh & Aart
It does "in-view and cross-view checks to Qualib Enable your IP"??? It
has 300+ IP validation checks across 33 formats At this DAC'23 they'll
be showing its zippy parsing speeds with Calibre DRC. Used by 50+ semi
companies with public endorsements from STMicro, Samsung, and Mixel.
(booth 2521) Ask for Siddharth Ravikumar. Freebee: espresso & beer
---- ---- ---- ---- ---- ---- ---- ---- ----
Keysight HUB (former ClioSoft) manages IP enterprise wide. HUB Crawler
crawls internal IP repositories and design data management solutions to
locate and catalog enterprise-wide IP. HUB Security does traceabilty
and geofencing capabilities for IP security and export controls.
Full hierarchical traceability for the Bill-of-Materials (BOM) through
the silicon lifecycle from SoCs to chiplets. "We got lots of customers."
(booth 1531) Ask for Karim Khalfan. Freebie: pens
Keysight SOS7 (formerly ClioSoft) does HW configuration mgmt
and rev control for Virtuoso, Laker, Custom Compiler, and Keysight ADS.
Built-in IP management and reuse. Soft integrations with in-house
flows. Better security, improved IP traceability, Jenkins integrations.
"SOS7 does cloud, too!" Sparce populate. Hooks to JIRA, Trac, Bugzilla.
Claims new technology results in "97.3% disk file storage savings."
Google, Analog Devices, Infineon, Toshiba, Marvell, TSMC, HiSilicon
(booth 1531) Ask for Karim Khalfan. Freebie: pens
Empyrean Qualib also does format consistency checks on hard IP?
But whatever it is, Marvell, SMIC, and HiSilicon use Qualib.
(booth 2513) Ask for Jason Xing. Freebie: fluffy animal
Amazon AWS might be the #1 host for EDA tools. (booth 1532)
Microsoft Azure might be the #2 host for EDA tools. (booth 2435)
Google Cloud is a distant #3 host for EDA tools. (booth 1445)
IBM Cloud is very distant #4 mostly for IBM tools. Not at DAC.
Alibaba Cloud only in China and is unknown in EDA. Not at DAC.
EDITOR'S NOTE: Again my Troublemaker's Panel is 3:00 in the DAC Pavillion. - John
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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