( ESNUG 423 Item 12 ) ------------------------------------------- [02/26/04]
Subject: 90 nm, Open Access, Oasis (GDSIII) Questions
Given the tight schedules/complexity of designs in the 130 nm and
sub-130 nm nodes, is the EDA industry looking at supporting "incremental"
aspects to various pieces of the flow. This primarily needs to be addressed
in the layout/routing and design validation phases.
---- ---- ---- ---- ---- ---- ----
1. Do you agree that evolutionary P&R enhancements will not be able to
attack the challenges coming with smaller geometries?
If so, what part of the flow will the industry need to focus on to
successfully address this:
A) Architectural Tool Improvements
B) Logic Tool Improvements
C) Physical Tool Improvements
D) None of the above (i.e. something entirely new)
2. What is the largest issue with integrating 3rd party IP and what is
needed to overcome the issue.
---- ---- ---- ---- ---- ---- ----
For those companies in the "prediction" business (i.e. crosstalk, voltage
drop etc.) -- What kind of silicon correlation have you done? Are you
aware that your users did?
---- ---- ---- ---- ---- ---- ----
I'd ask them how anyone is supposed to create a 1B transistor design?
Doesn't it point to needing a building block approach; or an FPGA (or
some generic part with parameterizable pieces) or something else. It
seems that even if someone had the tools to design 1Bt's, it'd still
be too daunting to start from scratch.
Seems like we're becoming a mature industry. How many times does a
car company start from scratch?
---- ---- ---- ---- ---- ---- ----
Who do the CEOs think will actually be doing 90nm designs? Given the
monster designs needing verification and implementation tricks/tools
that don't yet exist, 90nm is out of reach for majority of silicon
builders. I can think of Intel, IBM, but the list gets real short real
fast. So, who do the EDA heads think will be actually targetting 90nm
and why and when?
---- ---- ---- ---- ---- ---- ----
I was at DATE-04 last week and the issue of how much it costs to design in
a techno like 90nm was not adequately answered. Costs range $20M-$50M
for a single chip design were mentioned. Solutions like IP reuse, platform
design and various high level design tools were talked about, but the
consequent saving in design cost wasn't. My question is: If you design in
90nm and use all the suggested options to reduce design cost like IP reuse,
platform design and high level design tools, what will be the saving in
design cost? What will be the associated added cost to buy in the IP,
platform, tools etc?
---- ---- ---- ---- ---- ---- ----
How does the EDA industry expect to provide solutions that addresses DSM
issues that does not include Si qualification as part of the validation
of capabilities in their tools?
the EDA industry has been 1-2 years late on average in addressing the DSM
issues (DFM, Metal variation, core noise, statistical analysis, etc.) how
will they catch up moving forward, and present capabilities when they are
needed? will we see more investment in R&D and close working relations
with Fabs?
---- ---- ---- ---- ---- ---- ----
I would be tempted to ask what is being done to address synthesis in
very high frequency designs. I'm not convinced that wire and gate delay
are being treated appropriately in 4GHz+ designs and am therefore
curious about whether there will be algorithm changes to accommodate
this.
---- ---- ---- ---- ---- ---- ----
It might be fun to ask them how they will respond to the growing linkage
between back-end design, reticle enhancement technology and litho. From
what I hear (a lot--I'm helping out at SPIE this week) RET techniques are
all over the place even for 90 nm gate masks, and they are not converging.
But the way you do the reticle enhancement depends on the litho equipment
that will be used, and it influences how you do the layout of the
cells -- sometimes, it even influences the cell assembly process. Different
kinds of phase shifting and different kinds of assist features have
different design rules, etc. Not only do the tools have to be able to
handle the different sets of rules (which can change for different areas
on the same die) but ideally, they'd be able to pick the best RET and
lithography combination for each path to minimize cost while achieving
target performance.
- Ron Wilson of EE Times
---- ---- ---- ---- ---- ---- ----
My questions are mainly directed towards addressing the next deep sub-micron
and design integration challenges:
1) strategy for power (static/dynamic) estimation/management
at different levels:
1.1) RTL level
1.2) design planning level (chip level)
1.3) place/route level
1.4) cell level
2) gigascale integration (capacity)
2.1) design planning, place&route
2.2) timing and design integrity closure
2.3) extraction methodology
2.4) STA methodology
2.5) overall design support model
3) ways to shorten the overall design cycle
4) Plans to support the platform approaches.
---- ---- ---- ---- ---- ---- ----
What killer applications do they see that have the potential do drive
demand at 90 nanometer and below given the high costs of manufacturing
and higher risks at these feature sizes?
---- ---- ---- ---- ---- ---- ----
At DATE's CEO Panel, there was an audience question to the CEO's on
their commitment of support to OpenAccess (which as you know Si2
facilitates for the OA Coalition and is a huge customer-led industry
effort). Ray and Wally did not surprise with their "We fully support
OpenAccess" comments, however the big surprise -- and ensuing buzz --
was that Aart also took the mic and also answered "I support
OpenAccess". This left a murmur in the crowd and at the EDAC reception
about what Aart really means by this, and what it portends for Synopsys
strategy and direction, and lots of "second-guessing" in terms of
MilkyWay's future, etc.
It might be "edgy" to ask about what Aart really meant, and also what
they all think about these customer-driven collaborative / standards
efforts -- are they a nuisance? Do they feel they lose control? Why
should EDA suppliers really embrace anything that was not invented by
their own EDA industry?
---- ---- ---- ---- ---- ---- ----
When are you all planning to fully adopt Open Access?
---- ---- ---- ---- ---- ---- ----
Realistically, when are they going to support the Oasis (GDSIII) new
streaming format or fully adopt it? Are they going to put the effort in
to it or are they going to wait and see like everyone else?
Just so that you know, most people at SPIE are asking the EDA vendors if
they are going to support Oasis and when? But no one that I know has any
working files except Steffen Schulze at Mentor Graphics. Everyone is of
the mind that it is 2-3 years out?
In all fairness, I have to say that I work for a company with a competing
technology, a software compressor for GDSII files.
---- ---- ---- ---- ---- ---- ----
The foundry and fab bosses tell us that at 90nm and 65nm the big problem is
sub-threshold leakage. This partially or completely negates the traditional
benefits of the shrink. So what are EDA firms doing to cope with this
unknown factor in their front end and back end tools?
With the vast numbers of transistor available at 90nm and beyond, will the
EDA industry slip behind or be able to keep up with the silicon?
- Richard Ball of Electronics Weekly
---- ---- ---- ---- ---- ---- ----
Between OPC, parasistics & noise at 90 nm & less, it's beginning to look
like many of the advantages of hierarchical design are evaporating. How do
the various companies plan on attacking the capacity problem of
designing & verifying multi-million gate designs virtually flat?
---- ---- ---- ---- ---- ---- ----
I would like to ask EDA vendors how to address power reduction
(active/leakage power) for 90nm technology, it becomes the top agenda for
90nm technology. However, most companies discuss about multi-Vt flow
(for leakage reduction only), they never address active power solution yet,
please discuss this topics with them.
Moreover, I also want to know how they handle the DFM issues, we have
talked about this issue before last year DAC, however, no commercial tool
is available to address this problem yet. I have seen a lot of presentation
materials but it is targeted for small chip design (> 100K gate).
---- ---- ---- ---- ---- ---- ----
I would speak about the changing business case for a full-custom integrated
circuit. It would seem the rising cost to design and prototype next
generation microchips (say, through to 2010) could make them unreachable by
a growing number of small and medium enterprises. Perhaps only the
Intels and IBMs of the world will have the NRE capacity to design and
prototype a sub-45nm chip. That means the rest of us will have to
innovate and compete via system-level design, programmable SOCs and
multi-die microsystems made with some off-the-shelf 45nm parts (among other
parts such as sensors and actuators). This problem is a lot bigger than
the anticipated, traditional, incremental improvements in EDA expected over
the next decade, and no disruptive technology of any kind is visible to
solve it. Yes, the cost per transistor continues to decrease. But the
NRE to design and prototype a device is drifting out of reach. What are
the EDA companies doing now to monitor the situation, and prepare should
this scenario pan out?
---- ---- ---- ---- ---- ---- ----
Why do the EDA seats for 0.18u cost the same as for 0.09u? I would 10X
difference as the amount of R&D is about 10x more.
---- ---- ---- ---- ---- ---- ----
After visiting DATE I am asking myself this question.
How much of the signal integrity checks are actually needed at the 130 nm
node? Many library vendors do not have views for the tools and still "many"
successful chips have been taped out. In other words: Is the signal
integrity issue currently a hype by the EDA vendors or is it addressing
a real problem?
|
|
