( ESNUG 446 Item 6 ) -------------------------------------------- [09/01/05]
From: Stefan Sandstrom <stefan.sandstrom=user domain=axis pot calm>
Subject: My Life Using VCS, Leda, DC, and System Verilog in a Real Project
Hi John,
I would like to give your readers our experiences on using System Verilog
with VCS, Leda, and Design Compiler on a real life project. We've been
developing CPU cores and System On Chips (SOCs) for many years now. Our
first SOC, ETRAX was used in our print server products as early as 1993.
Today we are focusing on SOCs for network cameras and video servers. Our
last SOC used a few million gates in 0.13 um.
In our previous project we used Verilog plus a homebrewed pre-processor
that implemented System Verilog (ish) interfaces. Our experience with this
approach was very positive. The interface concept really saves a lot of
time and frustration. The two main benefits we saw were:
- The use of well defined interfaces.
We used protocol checkers (written in an FSM-like format that was
translated into Verilog) to check for illegal behavior on some design
global interfaces. This lead to significantly fewer problems when
connecting different subsystems together the first time.
- The size of the RTL code was drastically reduced.
For the entire project, the RTL code size was reduced by 40% with the
use of interfaces (compared to the interfaces being expanded to
"standard" Verilog). For specific subsystems the same number could
be up to 50% off. A lot of typing and typos saved there!
Encouraged by these experiences, we have today gone for System Verilog all
the way when it comes to RTL design. We've also started to use System
Verilog Assertions (SVA) fairly extensively for all new code.
The tools we use are: VCS for simulation, Leda for linting and Design
Compiler for synthesis.
Using real System Verilog tools instead of a pre-processor made debugging
easier as the tools refer to the actual source code instead of a pre-
processed version of it.
Even though the syntax for interfaces has changed slightly since we wrote
our pre-processor, the transition to System Verilog has been mostly smooth.
Our protocol checkers had to be rewritten as assertions inside the interface
definitions. That way the checks are present wherever an interface is used.
No specific instantiation of a checker (that might be forgotten, or worse,
deliberately left out) is needed.
From what we've seen, the largest boosts from moving to System Verilog as a
design language comes from the more advanced data types and assertions.
Using the more advanced data types, like "enums" for FSM state encoding and
"structs" for grouping data together makes the code easier to read,
maintain and debug. For example, the FSM state names automatically shows
up when tracing signals. Also, signed data types makes life easier when
dealing with signed arithmetic.
The SVA assertions helped a lot in finding bugs faster. Our experience is
that the quality of a subsystem improves much faster when writing assertions
along with the code.
VCS, DC, and Leda:
So how have the tools worked?
When we first started to use VCS for System Verilog, about a year ago,
there were quite a few quirks in the tool. Partly because some important
features were missing, partly because of bugs. But with VCS 7.2 (released
this January) the maturity of the design subset of System Verilog as well
as for System Verilog assertions has improved. We still do run into
occasional bugs, though not often.
As for Design Compiler, the level of maturity for System Verilog is still
somewhat lower than for VCS. Still, today DC can fully synthesize System
Verilog code to gates.
We use Leda to check that our System Verilog code is sound. Especially
before synthesizing as it avoids DC runs aborted by bad RTL code.
The System Verilog support in Leda should be the same as in VCS, but the
two tools do not always agree on what is correct code. Also, code that is
synthesizable according to Leda is not always accepted by DC. Apart from
that, Leda does catch a fair amount of mistakes in the System Verilog code.
The bottom line for us is that switching to System Verilog has been a
success so far. Both design and verification has become more efficient.
In the future we plan to use more advanced System Verilog features,
especially for testbenches.
- Stefan Sandstrom
Axis Communication Lund, Sweden
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