( ESNUG 450 Item 11 ) -------------------------------------------- [01/25/06]
Subject: ( DVcon 05 #15 ) Four users gush about Cadence Palladium emulation
> Skim off those 76% no's and you get the 2005 emulator/accelerator use.
>
> 2005 - Cadence Palladium : ############################## 59%
> Verisity Axis : ########## 20%
> Mentor IKOS/Celaro/Vsta : ################ 31%
> EVE ZeBu : ####### 15%
> ProDesign : ### 6%
> Aptix : ## 4%
> Tharas Hammer : 0%
> Pittsburgh Sim : 0%
> Aldec Riviera-IPT : 0%
>
> Holy moley! Cadence Palladium jumped waaaaaay up from 39% to 59%! Whoa!
>
> - from http://www.deepchip.com/items/dvcon05-15.html
From: Pierre Lieutaud <pierre.lieutaud=usr domain=philips hot mom>
Hi, John,
We spent 6 months evaluating Palladium in-house, and then began leasing one
as of December 2003. Our criteria were to get two designs up and running to
provide "system/stress tests" that Palladium had to pass successfully.
We selected two mature designs and Cadence provided a full time application
engineer on site to port them to Palladium from our previous emulation
platform, which was Quickturn Mercury.
The first design took 11 days to port onto the machine, plus one day for DDR
model implementation. The second design, with a bonded out CPU core, took
only 5 days to port.
We design multimillion gate ICs, in the range from 1 to 4 million gates,
excluding RAMs & ROMs. We use Palladium as an integration tool, in a step by
step manner. We start with the basic infrastructure (CPU + mem controller)
and add new functions at each phase, up to the full IC. We don't currently
use Palladium for IP verification. We use it with NC-Sim for simulation
acceleration, and they work together smoothly.
The best things about Palladium are:
- No painful clock tree analysis
- No critical design partitioning
- Less effort to have a design up and running than on an FPGA based
system. We usually allocate only half resources for the job.
- Very fast compile time. One of our previous designs took 8 hours to
compile for an FPGA based system, while with Palladium it took only
40 minutes on a single SUN workstation.
- Extremely good debug capabilities; every net is visible and eventable.
This saves many recompilations when we are tracking bugs in an iterative
manner.
- Stable compilation. No more designs that suddenly stop working properly
because we've added 200 probes.
- Multiple user capability
- The larger design sizes that can be emulated. Cadence claims that they
can map design up to 128 M gates! Although we own a 10M chassis, we
never map a design bigger than 6 M gates.
Palladium's weaknesses:
- We'd like faster speed.
- Debug GUI could still be improved: better integration between netlist
browser and waveform viewer.
- HDL-ICE is not as reliable as traditional synthesis tools.
We also use an in-house FPGA prototyping system for speed and also for cost
optimization. Our goal is to provide our SW teams with platform choices
where they can develop early their software early, since Palladium can be
too slow for that purpose. We use the FPGA prototyping system for designs
less than 500k and for IPs.
We have been doing ICE for more than 10 years now, because it is the best
trade-off between design visibility and speed. We like the fact that with
Palladium we can simultaneously run sim-acceleration and In-Circuit
Emulation. It helps this tool be more cost effective.
It is a key tool of our pre-silicon verification activity, and I would
recommend it from a technical point of view. Cost is the hard point with
this kind tool. But with large and complex designs, it still provides
superior performance.
- Pierre Lieutaud
Philips Semiconductors Caen, France
---- ---- ---- ---- ---- ---- ----
From: Michael Shiuan <mshiuan=usr domain=s3graphics hot mom>
Hi, John,
We started using Palladium in 2002. We currently emulate designs in the
15 million to 30 million gate range.
Palladium's strengths:
- It's HDL-ICE compilation time is fast.
- Compilation time is fast once you got a good Partition Seed.
- Database sharing allows all target systems sharing the same database
in ICE and off-line debug modes.
Palladium's weaknesses:
- Symmetric download still has some issues.
- Machine Noise
We really liked Palladium's new PCIex Speedbridge used with PCIex-based
motherboard. Plus it supports multiple hosts for job load and memory
usage distribution. All in all, we have had a good experience with
Palladium and would recommend it.
- Michael Shiuan
S3 Graphics Fremont, CA
---- ---- ---- ---- ---- ---- ----
From: Tom Paulson <tom.paulson=usr domain=qlogic hot mom>
Hi, John,
We are very satisfied with Palladium. Version 1.2 of the Palladium SW
seems faster than the earlier version 1.1. The verification cycle of
finding a bug, re-synthesizing, re-compiling and re-running is less than
an hour for some of our designs.
Its Turbo Debug is great! FullVision gives us access to all signal points
for the waveform without having to specify them at run time. It is also
very fast, it takes only minutes to get small traces and 5-10 minutes to
get a large trace. Obviously this speeds debug.
We are now using VHDL for the DUT and Verilog for the testbench. We are
also using a technology library (supplied by our fab) with models for the
Palladium. All of this is new for us and is working very well. It is very
easy to synthesize both VHDL and Verilog together, and the vendor library
was also very easy to synthesize with our design.
One approach that I have found helpful with Palladium is to create a memory
that saves statistics as we run our simulations. We can then write the
memory to a file at the end of the simulation, and analyze the results.
The Palladium continues to out perform all other simulators with our smaller
designs running at 1.2 MHZ. This improves our capability to verify ASIC's.
- Tom Paulson
QLogic Corporation Eden Prairie, MN
---- ---- ---- ---- ---- ---- ----
From: [ Chicken Man ]
Hi, John,
Palladium's biggest strengths are the support, hardware stability, fast
compile times, performance with fully synthesizable testbench and the
possibility to connect to the SystemC world via QTI. Where it needs help
is the debugging tool and the download speed of waveform data. They
need work.
I would rate my experience with Palladium as very positive particularly in
the area of transaction based emulation with SystemC over QTI. Please keep
me anonymous.
- [ Chicken Man ]
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