( ESNUG 451 Item 8 ) -------------------------------------------- [02/08/06]
Subject: ( ESNUG 450 #8 ) This is exactly why Synopsys created IC Compiler
> I'm an STA engineer at Intel Israel and we have recently implemented a
> new method for adding margins to our design. Our flow is based entirely
> on Synopsys tools and until recently we modeled margins (such as PVT
> variations, aging, etc...) in our design using fixed uncertainty values.
> We found this method to be overly pessimistic, so we developed a new
> method that defines derate factors instead of a fixed number.
>
> What I'd like to learn is how other designers add such margins to their
> designs.
>
> - Yiftach Benjamini
> Intel Communication Group Haifa, Israel
From: <neilm=user domain=synopsys spot calm>
Hi, John,
To deal with variability, IC Compiler supports concurrent multi-scenario
analysis and optimization.
A "scenario" refers to a mode and/or corner that can be analyzed or
optimized. A mode is a functional state (e.g.: test mode, sleep mode,
mission mode) defined by a set of clocks, supply voltages, timing
constraints, and libraries. It can also have annotated data such as SDF
or parasitics files. A corner is defined as a set of libraries
characterized for process, voltage and temperature variations. Corners
are not dependent on functional settings, but rather result from process
variations during manufacturing along with voltage and temperature
variations in the environment in which the chip will operate.
It is also useful to understand what "concurrent" really means. Some
approaches are actually automated sequential techniques or a merging
approach where the constraints are merged into a single super-constraint
in order to achieve compliance across all scenarios. Sequential
optimization like this can lead to the "ping-pong" effect and lack of
convergence. Merging all the corners into a single worst case condition
gives unacceptable quality of results.
Our Multi-Corner, Multi-Mode (MCMM) solution adopted in IC Compiler does
a true concurrent analysis & optimization. Timing analysis is carried out
simultaneously on all mode/corner scenarios. The optimizations operate
based on costing of the worst violations for setup, hold and DRC across
all scenarios. This authentic concurrent implementation is faster and
gives significantly better results than the sequential or merging
techniques.
To run MCMM in IC Compiler v1.1 the 'icc_shell' is invoked with the
'-mv_mode' switch as follows:
$ icc_shell -mv_mode -f run.tcl
IC Compiler has a suite of commands to define and manage scenarios,
including:
icc_shell> create_scenario (creates a new scenario)
icc_shell> set_tlu_plus_files (TLU+ to be used in current scenario)
icc_shell> set_operating_conditions (OCs to be used in current scenario)
icc_shell> save_mw_cel - scenario (saves design w/ scenarios in Milkyway)
The timing and constraint reports in IC Compiler show worst case timing
across all scenarios. For example:
icc_shell> report_qor
****************************************
Report : qor
Design : DESIGN1
Version: X-2005.12-ICC1.1
Date : Thu Dec 15 20:55:59 2005
****************************************
Scenario 's1'
Timing Path Group 'reg2reg'
-----------------------------------
Levels of Logic: 33.00
Critical Path Length: 694.62
Critical Path Slack: -144.52
Critical Path Clk Period: 650.00
Total Negative Slack: -4533.01
No. of Violating Paths: 136.00
-----------------------------------
Scenario 's2'
Timing Path Group 'reg2reg'
-----------------------------------
Levels of Logic: 32.00
Critical Path Length: 393.61
Critical Path Slack: 61.18
Critical Path Clk Period: 500.00
Total Negative Slack: 0.00
No. of Violating Paths: 0.00
-----------------------------------
****************************************
Timing analysis can be performed in one of two ways -- a traditional min/max
methodology or via the PrimeTime-like early/late analysis approach utilizing
the on-chip variation (OCV) switch in the "set_operating_conditions" command.
MCMM scenarios support up to two TLU+ files (min & max) for extraction whilst
the operating conditions support min/max libraries or multi-voltage libs.
IC Compiler also supports global temperature scaling. There's a 20 page app
note available that describes in detail the MCMM setup requirements.
I would also encourage Yiftach to talk to our R&D experts who will be at our
Design For Yield (DFY) seminar at SNUG-Israel on Feb 28, 2006 in Herzliya.
- Neil Moore
Synopsys IC Compiler CAE Sunnyvale, CA
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