( ESNUG 457 Item 4 ) -------------------------------------------- [10/05/06]
Subject: George explains his claim that Bluespec is ESL while Forte is RTL
> There's no doubt that Mentor Catapult C and Forte Cynthesizer each offer
> interesting algorithmic synthesis solutions. But while they may be good
> for DSP filters, FFTs, and audio uPs, these algorithmic synthesis tools
> don't offer a significant advantage over Verilog or VHDL for the bulk of
> gates that are shipped today, including microcontrollers, DMA controllers,
> cache and memory controllers, bus/switch interconnects, bus interfaces,
> network/link layer controllers, sorting/queuing engines, finite state
> machines, processors (whether CISC/RISC/DSP/graphics), etc.
>
> This is because when it comes to designs with control logic and complex
> datapaths (which I define as those datapaths with control complexity to
> them such as bypassing, MUXing, feedback, and stalling) unless you are
> using Bluespec, you're still dealing with RTL.
>
> I hope by now, post-DAC (unless you still mistakenly think ESL is meant to
> be only for trivially parallelized DSP SW algorithms) for you ESL should
> certainly now include high-level synthesis solutions for control logic and
> complex datapaths. Bluespec currently is the only one with that solution.
>
> - from http://www.deepchip.com/wiretap/060927.html
From: George Harper <gharper=user domain=bluespec spot mom>
Hi, John,
Hey, I'm not claiming that we are the only people doing control logic and
complex datapaths, just that Bluespec is the only one doing it at the ESL
level. Regardless of the language (for example SystemC), all the other
control logic synthesis solutions are dealing with RTL. You can get a
taste of this by comparing a piece of Forte SystemC code with that of an
equivalent Bluespec implementation.
So yes, Forte can "support" control logic. Brett Cline recently said:
"What happens is that there are vendors out there that try to label
us as only being able to handle data path and algorithms. It turns
out that this is not true. We can handle complex control. If you
write an 'if' statement, you have written control. 'If-then-else'
is a control statement. A 'case' statement is control."
Brett's implication is that because their tool can do 'if-then-else'/'case',
Forte can handle complex control. Of course, the same argument would apply
to RTL, because Verilog and VHDL both do conditionals. So, what does this
offer over your plain olde standard Verilog or VHDL? Nothing.
As the old saying about roses goes, that which we call RTL by any other name
would still be RTL. Brett himself describes his own SystemC-based control
logic as RTL-like. In the same interview, Brett added:
"When you start writing a design that is 90% control based, where you
are writing 'if-then-else', the code you are writing looks a lot like
Verilog code. For those customers advancing immediately to a SystemC
based design flow or a C based design flow may not provide the same
ROI level as the customer who has a mostly algorithmic description."
Here's where it would help to compare some Forte vs. Bluespec code. The
only Forte code I was able to find was from their technical white paper
called "Doing Behavioral Design the Right Way Minimizes Verification":
SC_MODULE(mod_A) {
...
sc_out> out;
sc_in out_rdy;
sc_out out_vld;
...
};
void mod_A::entry()
{
if (!rst) {
out.write(0);
out_vld = 0;
wait(1);
}
while (true) {
...
y = f(...);
do {
wait(1);
} while (!out_rdy);
out_vld = 1;
out.write( y );
wait(1);
out_vld = 0;
}
}
SC_MODULE(mod_B) {
...
sc_out> out;
sc_out> out_rdy;
sc_in> out_vld;
...
};
void mod_B::entry()
{
if (!rst) {
out_rdy = 0;
wait(1);
}
while (true) {
...
out_rdy = 1;
do {
wait(1);
} while (!out_vld);
x = out.read();
out_rdy = 0;
...
}
}
Here's the same algorithm in Bluespec SystemVerilog code. We also support
SystemC; the same algorithm in SystemC would equally succinct.
module mod_A ();
...
intfc_B dut();
mod_B the_dut (dut);
rule foo_bar;
...
// In contrast, sending is simple. No need to check the
// readiness of the receiver NOR communicate the validness
// of the data to send
y <= f(...)
dut.writeval (y); ...
endrule
...
endmodule
interface intfc_B;
method Action writeval (bit[31:0] out);
endinterface;
module mod_B (intfc_B)
Reg#(Bool) out_rdy();
mkReg#(False) the_rdy_reg (out_rdy);
...
out_rdy <= True; // A rule sets this when ready to receive
...
method Action writeval(out) if (out_rdy);
x <= out; // The receiver need not check when
// the sender's data is valid
out_rdy <= False;
endmethod
endmodule
What both snippets show is code for doing interfaces that are latency
independent. I've tried to keep this an apples-to-apples comparison. It
required filling in some of the details of Forte's code, as they showed
the full implementation of only one side of the interface -- though they
had code excerpts for both sides.
Contrast the succinctness and level of details in these equivalent Forte
and Bluespec code fragments. And this is a simple example!; more complex
algorithms would show an even wider diverging levels of complexity.
As illustrated by Brett's example, there's a big difference between
supporting control logic and complex datapaths AND providing any value
over standard (Verilog/VHDL/SystemVerilog) RTL. Bluespec is a simpler and
more scalable way of managing complex concurrency & interface protocols
vs. RTL. We are also the only one significantly improving the design of
control logic and complex datapaths. Such troublesome designs are:
- The hardest to get right. Managing complex concurrency with lots of
shared resources (both local and across chip) is very hard to
implement correctly. Think about the challenges properly managing
back pressure, interface protocols, race conditions, deadlock/livelock
conditions...
- The areas where most of the bugs (especially the subtle ones that
later bite you) reside.
- The most prominent by far. One of our customers surveyed their IP
development roadmap and found that designs with control logic and
complex datapaths represented 90% of their planned projects.
This is where Bluespec shines. Everything else is just RTL.
- George Harper
Bluespec, Inc. Waltham, MA
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