( ESNUG 466 Item 8 ) -------------------------------------------- [07/12/07]
Subject: References
[1] "IEEE P1364-2005 standard for the Verilog Hardware Description
Language", IEEE, Pascataway, New Jersey, 2001. ISBN 0-7381-4851-2.
[2] "IEEE 1800-2005 standard for the System Verilog Hardware
Description and Verification Language", IEEE, Pascataway, New Jersey,
2001. ISBN 0- 7381-4811-3.
[3] "System Verilog for Design: A Guide to Using System Verilog for
Hardware Design and Modeling", by Stuart Sutherland, Simon Davidmann
and Peter Flake. Published by Springer, Boston, MA, 2004, ISBN:
0-4020-7530-8.
[4] "Signed Arithmetic in Verilog 2001 -- Opportunities and Hazards",
by Dr. Greg Tumbush. Published in the proceedings of DVCon, 2005.
[5] "full_case parallel_case, the Evil Twins of Verilog Synthesis",
by Clifford Cummings. Published in the proceedings of SNUG Boston,
1999.
[6] "System Verilog Saves the Day -- the Evil Twins are Defeated! 'unique'
and 'priority' are the new Heroes", by Stuart Sutherland. Published in
the proceedings of SNUG San Jose, 2005.
[7] "System Verilog's priority & unique - A Solution to Verilog's
'full_case' & 'parallel_case' Evil Twins!", by Clifford Cummings.
Published in the proceedings of SNUG Israel, 2005.
[8] "Being Assertive With Your X", by Don Mills. Published in the
proceedings of SNUG San Jose, 2004.
[9] "System Verilog Assertions are for Design Engineers, Too", by Don
Mills and Stuart Sutherland. Published in the proceedings of SNUG San
Jose, 2006.
[10] "RTL Coding Styles That Yield Simulation and Synthesis
Mismatches", by Don Mills and Clifford Cummings. Published in the
proceedings of SNUG San Jose, 1999, and SNUG Europe, 2001.
Index
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